Provided is a system for building and validating an application (including e.g., various software versions and revisions, programming languages, code segments, among other examples) without any scripting required by a system user. In one embodiment, an SDLC system is configured to construct a build and test environment, by automatically analyzing a submitted project. The build environment is configured to assemble existing user code, for example, to generate an application to test. Code building can include any one or more of code compilation, assembly, and code interpretation. The system can include a user interface provided to clients, users, and/or customer environments to facilitate user interaction and control of build and test validation. The system can accept user specification of configurations that controls the way the system runs the user's tests. The system can also provide flexible billing models for different customers.

System of distributed software quality improvement

Our new technique for estimating transition probabilities of internal signals in combinational circuits uses Markov chains and reconvergence regions. To efficiently implement the computation, we use ROBDDs (reduced, ordered binary decision diagrams). Accounting for temporal dependence of signals, multiple concurrent transitions, and mutual dependence of internal signals, the technique provides an exact computation for small circuits and an approximate estimate for large circuits. Experimental results show the estimation technique is fast with only small inaccuracies.

Fast power estimation of large circuits

In order to process a program by parallel processing using a plurality of processors, the program is divided (34) into a plurality of partial programs. Then one or more expressions are devided (38), the or each expression expressing a relationship between the partial programs, such as which can be executed independently and which require the execution of another partial program. The expression or expressions can then be investigated (37) to determine which has a desired characteristic, such as a characteristic corresponding to uniform loading of the processors. The expression can also be varied, to give more options for the selection of the expression with the desired characteristic. Then the partial programs can be distributed (14,15) to the processors on the basis of the relationship corresponding to the expression which has the desired characteristic. Furthermore, when the partial programs are being executed by the processors, any processor which has completed its processing broadcasts a signal to the other processors, which may then re-assign one or more of their partial programs. In this way, parallel processing can be carried out quickly, with substantially uniform loading of the processors.

A method of processing a program by parallel processing, and a processing unit thereof

In the framework of fully permutable loops, tiling has been studied extensively as a source-to-source program transformation. We build upon recent results by Hogsted, Carter, and Ferrante (1997), who aim at determining the cumulated idle time spent by all processors while executing the partitioned (tiled) computation domain. We propose new, much shorter proofs of all their results and extend these in several important directions. More precisely, we provide an accurate solution for all values of the rise parameter that relates the shape of the iteration space to that of the tiles, and for all possible distributions of the tiles to processors. In contrast, the authors in Hogsted, Carter, and Ferrante (1997) deal only with a limited number of cases and provide upper bounds rather than exact formulas.

Determining the Idle Time of a Tiling: New Results

In the framework of perfect loop nests with uniform dependences, tiling has been extensively studied as a source-to-source program transformation. Little work has been devoted to the mapping and scheduling of the tiles on to physical processors. We present several new results in the context of limited computational resources, and assuming communication-computation overlap. In particular, under some reasonable assumptions, we derive the optimal mapping and scheduling of tiles to physical processors.

/pdf/tiling-with-limited-resources-2o5akjizu0.pdf

Tiling with limited resources

An important issue for the efficient use of multiprocessor systems is the assignment of parallel processors to nested parallel loops. It is desirable for a processor assignment algorithm to be fast and always generate an optimal processor assignment. The paper proposes two efficient algorithms to decide the optimal number of processors assigned to each individual loop. Efficient parallel counterparts of these two algorithms are also presented. These algorithms not only always generate an optimal processor assignment, but also are much faster than the exiting optimal algorithm in the literature. The paper discusses improving the performance of parallel execution by transforming a nested parallel loop into a semantically equivalent one. Three loop transformations are investigated. It is observed that, in most cases, the parallel execution time is improved after applying these transformations. >

Efficient processor assignment algorithms and loop transformations for executing nested parallel loops on multiprocessors

Tiling Nested Loops into Maximal Rectangular Blocks

We investigate fault-tolerant routing schemes which aim at using low number of virtual channels in wormhole-routed mesh networks. The faults under consideration are rectangular block faults, which are suitable for modeling faults on board level in networks with grid structures. There is no restriction on the number of faults. The concepts of f -ring and f -chain are used in our scheme. Messages are routed minimally when not blocked by faults and are routed along the boundaries of the faults encountered. Only three virtual channels and local knowledge of faults are required for our routing scheme to be correct, deadlock- and livelock-free. By allocating virtual channels to messages carefully, all virtual channels have the potential to be used by messages; hence, none of the virtual channels and its associated hardware is wasted.

A fault-tolerant routing algorithm for wormhole routed meshes

In this paper, the problem of partitioning of parallel programs for execution on multiprocessors is investigated. By assuming run-time scheduling approaches, the static partitioning problems are formulated and solved in the context of a structured program representation model, in which a program is assumed to be composed of parallel loops. The structured partitioning problem is then defined as the problem of partitioning each parallel loop into appropriate number of tasks such that the program execution time is minimized in some sense. The worst case of the program execution cost is adopted as the minimization criterion, so the results obtained in this paper are guaranteed to be within some performance bound. Two algorithms are developed to solve this problem. The first algorithm using a prune-and-search technique can find the optimal partition, while the second algorithm can obtain a near optimal partition for the simplified partition problem in linear time. It is proved that the cost of the partition generated by the linear time algorithm is at most twice the cost of the optimal partition.

Structured partitioning of concurrent programs for execution on multiprocessors

Compiler Techniques for Extracting Loop-Level Parallelism.

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