Fault detection/diagnosis has become a crucial function of the battery management system (BMS) due to the increasing application of lithium-ion batteries (LIBs) in highly sophisticated and high-power applications to ensure the safe and reliable operation of the system. The application of Machine Learning (ML) in the BMS of LIB has long been adopted for efficient, reliable, accurate prediction of several important states of LIB such as state of charge, state of health and remaining useful life. Inspired by some of the promising features of ML-based techniques over the conventional LIB fault detection/diagnosis methods such as model-based, knowledge-based and signal processing-based techniques, ML-based data-driven methods have been a prime research focus in the last few years. This paper provides a comprehensive review exclusively on the state-of-the-art ML-based data-driven fault detection/diagnosis techniques to provide a ready reference and direction to the research community aiming towards developing an accurate, reliable, adaptive and easy to implement fault diagnosis strategy for the LIB system. Current issues of existing strategies and future challenges of LIB fault diagnosis are also explained for better understanding and guidance.

Machine Learning-Based Data-Driven Fault Detection/Diagnosis of Lithium-Ion Battery: A Critical Review

....................................................................................................... 8 ACKNOWLEDGEMENTS ............................................................................... 10 Abbreviations ..................................................................................................... 11 1  INTRODUCTION ..................................................................................... 12 1.1  Motivation .......................................................................................... 13 1.2  Methods and theories ......................................................................... 14 1.2.1  Determinacy Analysis ................................................................ 14 1.2.2  Generator of Hypotheses ............................................................ 16 1.2.3  Theory of Monotone Systems .................................................... 17 1.3  Research aims .................................................................................... 17 1.4  Overview of developments ................................................................ 18 1.5  Previously published work ................................................................. 21 1.6  Contribution of the thesis ................................................................... 22 1.7  Organisation of the thesis ................................................................... 22 2  THEORETICAL BACKGROUND ........................................................... 23 2.1  Data mining ........................................................................................ 23 2.2  Machine Learning .............................................................................. 24 2.2.1  Definitions of learning from examples ...................................... 25 2.3  Classification ..................................................................................... 26 2.3.1  Decision trees ............................................................................. 27 2.3.2  Classification rules ..................................................................... 28 2.4  Association rule mining ..................................................................... 30 2.4.1  Frequent itemsets ....................................................................... 31 2.4.2  Association rules ........................................................................ 34 2.5  Combining classification and association rules ................................. 38 2.6  Theory of Monotone Systems ............................................................ 41 2.6.1  Algorithm MONSA ................................................................... 42 2.7  Determinacy analysis ......................................................................... 50

From Determinacy Analysis to Zero Factor Free Determinacy Analysis and Universal Generator of Hypotheses: Development of Algorithms

Advanced machine learning techniques offer an unprecedented opportunity to increase the accuracy of board-level functional fault diagnosis and reduce product cost through successful repair. Ambiguous or incorrect diagnosis results lead to long debug times and even wrong repair actions, which significantly increase repair cost. We propose a smart diagnosis method based on multikernel support vector machines (MK-SVMs) and incremental learning. The MK-SVM method leverages a linear combination of single kernels to achieve accurate faulty-component classification based on the errors observed. The MK-SVMs thus generated can also be updated based on incremental learning, which allows the diagnosis system to quickly adapt to new error observations and provide even more accurate fault diagnosis. Two complex boards from industry, currently in volume production, are used to validate the proposed diagnosis approach in terms of diagnosis accuracy (success rate) and quantifiable improvements over previously proposed machine-learning methods based on several single-kernel SVMs and artificial neural networks.

Board-Level Functional Fault Diagnosis Using Multikernel Support Vector Machines and Incremental Learning

Introduction and Motivation -- State of the Art of Modelling and Simulation of the Physiological Systems -- Proposed Novel Generic Framework for Modelling the Bioelectrical Information -- Implementation of the Framework and the Experimental Results -- Conclusions.

A Parametric Framework for Modelling of Bioelectrical Signals

Mutation-Based Verification and Error Correction in High-Level Designs. Mutatsioonidel põhinev verifitseerimine ja vigade parandamine kõrgtaseme skeemides

In this paper, a new very fast fault simulation method to handle the X-fault model is proposed. The method is based on a two-phase procedure. In the first phase, a parallel exact critical path fault tracing is used to determine all the detected stuck-at faults in the circuit, and in the second phase a postprocess is launched which will determine the detectability of X-faults.

Parallel X-fault simulation with critical path tracing technique

The infrastructure of IJTAG can be utilized during operation to detect errors and make appropriate fault handling. This article describes an architecture where error latency and automation are important requirements.

Effective Scalable IEEE 1687 Instrumentation Network for Fault Management

IEEE 1687 (IJTAG) has been developed to enable flexible and automated access to the increasing number of embedded instruments in today's integrated circuits. These instruments enable efficient post-silicon validation, debugging, wafer sort, package test, burn-in, bring-up and manufacturing test of printed circuit board assemblies, power-on self-test, and in-field test. Current paper presents an overview of challenges as well as selected examples in the following topics around IEEE 1687 networks: (1) design to efficiently access the embedded instruments, (2) verification to ensure correctness, and (3) fault management at functions performed in-field through the product's life time.

/pdf/design-verification-and-application-of-ieee-1687-2ccgikab51.pdf

Design, Verification, and Application of IEEE 1687

This paper studies a new approach for board-level test based on synthesizable embedded instruments implementted on FPGA. This very recent methodology utilizes programmable logic devices (FPGA) that are usually available on modern PCBs to a large extent. The purpose of an embedded instrument is to carry out a vast portion of test application related procedures, perform measurement and configuration of system components thus minimizing the usage of external test equipment. By replacing traditional test and measurement equipment with embedded synthetic instruments it is possible not only to achieve the significant reduction of test costs but also facilitate high-speed and at-speed testing. We detail the motivation and classify the FPGA-based instrumentation into different categories based on the implementation and application domains. Experimental results show the efficiency of this approach.

FPGA-based synthetic instrumentation for board test

The paper describes asynchronous fault detection in silicon chips with network of embedded instruments based on IEEE P1687 IJTAG. This technique allows faster fault detection and localization by using asynchronous signal propagation from instruments to instrumentation network controller. The additional hardware is described, scenarios of operation including multiple simultaneous fault detection and localization are analysed.

Asynchronous Fault Detection in IEEE P1687 Instrument Network

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