In this paper ANT colony optimization algorithm has been proposed to solve FPGA routing in FPGA design architecture with minimum umbers of tracks per channel. In our method geometric FPGA routing task is transformed into a Boolean satisfiability (SAT) equation with the property that any assignment of input variables that satisfies the equation specifies a valid route. The satisfiability equation is then modeled as Constraint Satisfaction problem. Satisfying assignment for particular route will result in a valid routing and absence of a satisfying assignment implies that the layout is unroutable. In second phase of this method ant colony optimization algorithm is applied on the Boolean equation for solving routing alternatives utilizing approach of hard combinatorial optimization problems. The ACO based solution to SAT is then compared with the other SAT solver algorithms such as zChaff and GRASP. The experimental results suggested that the developed ant colony optimization algorithm is taking fewer amounts of time and minimum channel width to route a FPGA chip.

Ant Colony Optimization approach for Solving FPGA routing with minimum Channel Width

In this paper ANT colony optimization algorithm are used to solve geometric FPGA routing for a route based routing constraint model in FPGA design architecture which is a NP complete problem in nature and many conventional and heuristic algorithms have been developed and proposed for this problem . In this paper ant colony optimization algorithm is applied on the Boolean equation consist of the FPGA routing problem. The ACO based solution to SAT is then compared with the other SAT solver algorithms such as zChaff and GRASP. The experimental results suggest that the developed ant colony optimization algorithm has taken less CPU time as compared to zChaff and GRASP to route a FPGA circuit. This method is implemented and shown to be performed efficiently and can be extended to more complex circuits.

/pdf/solving-fpga-routing-using-ant-colony-optimization-with-48z4hojhzv.pdf

Solving FPGA Routing using Ant Colony Optimization with Minimum CPU Time

This paper is based on an ant colony optimization algorithm (ASDR) for solving FPGA routing for a route based routing constraint model in FPGA design architecture. I n this approach FPGA routing task is transformed into a Boolean Satisfiabilty (SAT) equation with the property that any assignment of input variables that satisfies the equation specifies a v alid route. The Satisfiability equation is then modeled as Constraint Satisfaction problem, which helps in reducing procedural programming. Satisfying assignment for particular route will result in a valid routing and absence of a satisfying assignment implies that the layout is unroutable. In second step ant colony optimization algorithm is applied on t he Boolean equation for solving routing alternatives utilizing approach of hard combinatorial optimization problems. The experimental results suggest that the developed ant colony optimization algorithm based router has taken extremely short CPU time as compared to classical Satisfiabilty based detailed router (SDR) and finds all possible routes even for large FPGA circuits.

/pdf/ant-colony-based-approach-for-solving-fpga-routing-3nr1v81hig.pdf

Ant Colony Based Approach for Solving FPGA routing

Classical Problems on any discipline of study has to undergo a series of alternative approaches at different points of time. Many experimental verification of fundamental theoretical results have to be framed in the domain of mathematical modeling based on iterative approaches. One such area of our interest is VLSI Design issue in particular Circuit Partitioning. We present here chronological order of different procedures based on variety of graph theoretical and optimization techniques. These fall into major classification of deterministic and Probabilistic tool kits. A clear cut understanding of these collection will facilitate the researchers engaged in this field for creditable contribution. Hypergraph method is better than the vertical and horizontal procedure in wing and cell partitioning .New type of hypergraph called unimodular hypergraph gives better results for VLSI Cell partitioning.

Review of Efficient and Innovative Mathematical Models on VLSI Circuit Partitioning

FPGAs are used for a wide range of applications, e.g. network communication, video communication and processing and cryptographic applications. It has been shown that FPGAs are suitable for the implementation of soft computing techniques like Neural Networks and Genetic Algorithms. In this work we have shown that Ant Colony Optimizations can also be implemented on FPGAs, leading to significant speedups in runtime compared to implementations in software on sequential machines. This paper presents an ant colony optimization algorithm for geometric FPGA routing for a route based routing constraint model in FPGA design architecture.

/pdf/optimized-fpga-routing-using-soft-computing-cjwhed3507.pdf

Optimized FPGA Routing using Soft Computing

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Optimized FPGA Routing using Soft Computing