Design consideration of vertical MOSFET with double gate structure on each side of insulating pillar for nanodevice applications is presented. The body doping effect on vertical channel for channel length, Lg = 50nm and analyzing its effect towards such small devices was successfully performed. The analysis continued with the comparative investigation of device performance with conventional planar MOSFET as scaling Lg down to 50nm. The final part evaluates the innovative design of incorporating dielectric pocket (DP) on top of vertical MOSFET turret with comprehensive device performance analysis as compared to standard vertical MOSFET in nano scale realm. An optimized body doping for enhanced performance of vertical MOSFET was revealed. The vicinity of DP near the drain end is found to reduce the charge sharing effects between source and drain that gives better gate control of the depletion region for short channel effect (SCE) suppression in nanodevice structure.

Performance Design and Simulation Analysis of Vertical Double Gate MOSFET (VDGM)

The computational analysis of ballistic saturation velocity for low-dimensional nano-devices was presented. The ballistic transport is predicted in the presence of high electric field for non-degenerate and degenerate regime. The saturation velocity is found to be ballistic regardless of the device dimensions. The intrinsic velocity limits this saturation velocity. It's does not sensitively depend on the ballistic or scattering-limited nature of the mobility. In the degenerate realm, the saturation velocity is shown to be the Fermi velocity that is independent of temperature but strongly dependent on carrier concentration. In the nondegenerate realm, the intrinsic velocity is the thermal velocity that depends only on the ambient temperature.

/pdf/computational-analysis-of-ballistic-saturation-velocity-in-28qvgmvei6.pdf

Computational analysis of ballistic saturation velocity in low-dimensional nano-MOSFET

Design consideration of vertical MOSFET with double gate structure on each side of insulating pillar for nanodevice applications is presented. The body doping effect on vertical channel for channel length, L g = 50nm and analyzing its effect towards such small devices was successfully performed. The analysis continued with the comparative investigation of device performance with conventional planar MOSFET as scaling L g down to 50nm. The final part evaluates the innovative design of incorporating dielectric pocket (DP) on top of vertical MOSFET turret with comprehensive device performance analysis as compared to standard vertical MOSFET in nanoscale realm. An optimized body doping for enhanced performance of vertical MOSFET was revealed. The vicinity of DP near the drain end is found to reduce the charge sharing effects between source and drain that gives better gate control of the depletion region for short channel effect (SCE) suppression in nanodevice structure.

Design and simulation analysis of nanoscale vertical MOSFET technology

Design and simulation analysis of vertical MOSFET structure with double gate structure on each side of insulating pillar for nanodevice applications is presented. The body doping effect on vertical channel for channel length, L g = 50nm and analyzing its effect towards such small devices was successfully performed. The analysis continued with the comparative investigation of device performance with conventional planar MOSFET as scaling L g down to 50nm. The final part evaluates the innovative design of incorporating dielectric pocket (DP) on top of vertical MOSFET turret with comprehensive device performance analysis as compared to standard vertical MOSFET in nanoscale realm. An optimized body doping for enhanced performance of vertical MOSFET was revealed. The vicinity of DP near the drain end is found to reduce the charge sharing effects between source and drain that gives better gate control of the depletion region for short channel effect (SCE) suppression in nanodevice structure.

Design and simulation analysis of vertical double-gate MOSFET (VDGM) structure for nano-device application

Silicon-based vertical MOSFETs

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Silicon-based vertical MOSFETs