Multi-core technology is a natural next step in delivering the benefits of Moore's law to computing platforms. On multi-core processors, the performance of many applications would be improved by parallel processing threads of codes using multi-threading techniques. This paper evaluates the performance of the multi-core Intel Xeon processors on the widely used basic linear algebra subprograms (BLAS). On two dual-core Intel Xeon processors with hyper-threading (HT) technology, our results show that a performance of around 20 GFLOPS is achieved on Level-3 (matrix-matrix operations) BLAS using multi-threading, SIMD, matrix blocking, and loop unrolling techniques. However, on a small size of Level-2 (matrix-vector operations) and Level-1 (vector operations) BLAS, the use of multi-threading technique speeds down the execution because of the thread creation overheads. Thus the use of Intel SIMD instruction set is the way to improve the performance of single-threaded Level-2 (6 GFLOPS) and level-1 BLAS (3 GFLOPS). When the problem size becomes large (cannot fit in L2 cache), the performance of the four Xeon cores with HT is less than 2 and 1 GFLOPS on Level-2 and level-1 BLAS, respectively, even though eight threads are executed in parallel.

Performance evaluation of multi-core intel xeon processors on basic linear algebra subprograms

This paper proposes a low-complexity vector-core called LcVc for executing both scalar and vector instructions on the same execution datapath. A unified register file in the decode stage is used for storing both scalar operands and vector elements. The execution stage accepts a new set of operands each cycle and produces a new result. Rather than issuing vector instruction (1-D operations) as a whole, each vector operation is issued sequentially with the existing scalar issue hardware. All loads and stores of registers take place from the data cache in the memory access stage in a rate of one element per clock cycle. The hardware required to support the enhanced vector capability is insignificant (few incrementers and multiplexers), which results in reducing the area per core and increasing the number of cores available in a given chip area. Three key features distinguish LcVc architecture: a unified ISA to scalar and vector processing, low cost, and simplicity of organization. The use of LcVc approximately doubles the speedup of executing vector/matrix kernels such as vector addition, vector scaling, SAXPY, dot-product, matrix-vector multiplication, and matrix-matrix multiplication.

LcVc: Low-complexity vector-core for executing scalar/vector instructions

Driven by increasing specialization, multicore integration will soon enable large-scale chip multiprocessors (CMPs) with many processing cores. In order to take advantage of increasingly parallel hardware, independent tasks must be expressed at a fine level of granularity to maximize the available parallelism and thus potential speedup. However, the efficiency of this approach depends on the runtime system, which is responsible for managing and distributing the tasks. In this paper, we present a hierarchically distributed task pool for task parallel programming on Cell processors. By storing subsets of the task pool in the local memories of the Synergistic Processing Elements (SPEs), access latency and thus overheads are greatly reduced. Our experiments show that only a worker-centric runtime system that utilizes the SPEs for both task creation and execution is suitable for exploiting fine-grained parallelism.

/pdf/exploiting-fine-grained-parallelism-on-cell-processors-pe5iskucsp.pdf

Exploiting fine-grained parallelism on cell processors

Emerging parallel architectures provide the means to efficiently handle more fine-grained and larger numbers of parallel tasks. However, software for parallel programming still does not take full advantage of these new possibilities, retaining the high cost associated with managing large numbers of threads. A significant percentage of this overhead can be attributed to operations on queues. In this paper, we present a methodology to efficiently create and enqueue large numbers of threads for execution. In combination with advances in computer architecture, this reduces cost of handling parallelism and allows applications to express their inherent parallelism in a more fine-grained manner. Our methodology is based on the notion of Batches of Threads, which are teams of threads that are used to insert and extract more than one objects simultaneously from queues. Thus, the cost of operations on queues is amortized among all members of a batch. We define an API, present its implementation in the NthLib threading library and demonstrate how it can be used in real applications. Our experimental evaluation clearly demonstrates that handling operations on queues improves significantly.

/pdf/department-of-electrical-and-computer-engineering-computer-26w54gti8y.pdf

Department of Electrical and Computer Engineering Computer Architecture and Parallel Systems Laboratory Handling Massive Parallelism Efficiently: Introducing Batches of Threads

Handling Massive Parallelism Efficiently: Introducing Batches of Threads.

Architectural Support for FineGrained Parallelism on Multicore Architectures

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Architectural Support for FineGrained Parallelism on Multicore Architectures