Sandhya Koteshwara
University of Minnesota
15 Papers
75 Citations
Sandhya Koteshwara is an academic researcher from University of Minnesota. The author has contributed to research in topics: Encryption & Authenticated encryption. The author has an hindex of 6, co-authored 15 publications. Previous affiliations of Sandhya Koteshwara include IBM.
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Papers
Comparative Study of Authenticated Encryption Targeting Lightweight IoT Applications
Sandhya Koteshwara,Amitabh Das +1 more
TL;DR: This new system can help operators of the power grid detect when device settings have been tampered, and help identified the context of a command.
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FPGA implementation and comparison of AES-GCM and Deoxys authenticated encryption schemes
Sandhya Koteshwara,Amitabh Das,Keshab K. Parhi +2 more
- 01 May 2017
TL;DR: This paper provides evaluations for Deoxys, a third round candidate from the ongoing Competition for Authenticated Encryption: Security, Applicability, and Robustness (CAESAR), and describes simplified flow diagrams and a detailed summary on the timing performance, area, memory and energy requirements of AES-GCM and deoxys.
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Incremental-Precision Based Feature Computation and Multi-Level Classification for Low-Energy Internet-of-Things
TL;DR: The proposed incremental-precision-based multi-level classification approach can reduce energy consumption by 35% while maintaining high sensitivity, or by about 50% at the expense of 15% degradation in sensitivity compared with similar approaches to seizure detection in literature.
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Architecture Optimization and Performance Comparison of Nonce-Misuse-Resistant Authenticated Encryption Algorithms
TL;DR: A performance comparison of new authenticated encryption algorithms which are aimed at providing better security and resource efficiency compared to existing standards and improve the security of existing AE standards by providing a critical property termed nonce-misuse resistance is presented.
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Performance comparison of AES-GCM-SIV and AES-GCM algorithms for authenticated encryption on FPGA platforms
Sandhya Koteshwara,Amitabh Das,Keshab K. Parhi +2 more
- 01 Oct 2017
TL;DR: A AES-GCM-SIV hardware implementation provides better security in terms of nonce-misuse resistance and greater flexibility with respect to reusability of main components of AES- GCM, and is the first paper which discusses a hardware implementation of this recently proposed algorithm.
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