This paper presents a two Nexys FPGAs implementation of a Least Significant Bit (LSB) watermarking applied on real-time speech signals over a serial communication system. The watermarking technique has been strengthened by means of a chaos-based encryption scheme for the used watermark image. The speech acquisition is performed using FPGA inbuilt microphone while the recovery has been realized through a loudspeaker as output device for the watermarked signal and VGA monitor for the watermark image respectively. The transmission of the watermarked signal has been implemented using Universal Asynchronous Receiver Transmitter (UART) serial protocol between two FPGA boards. The LSB IP-Cores developed and integrated in the watermarking prototype have been synthesized by means of a co-design approach using Vivado-HLS. The realized prototype has required performances of 1132 LUT area using a speed of 130 Mhz and a power consumption of no more than 159 mW. Lastly, good results have been obtained of watermarking imperceptibility and security with low robustness performances against signal processing and geometric cryptanalysis attacks. 

FPGA Implementation using Novel Co-Design Approach of Real-Time Speech Chaos based Crypto-Watermarking Prototype

Structured sparsity is an efficient way to prune the complexity of modern Machine Learning (ML) applications and to simplify the handling of sparse data in hardware. In such cases, the acceleration of structured-sparse ML models is handled by sparse systolic tensor arrays. The increasing prevalence of ML in safety-critical systems requires enhancing the sparse tensor arrays with online error detection for managing random hardware failures. Algorithm-based fault tolerance has been proposed as a low-cost mechanism to check online the result of computations against random hardware failures. In this work, we address a key architectural challenge with structured-sparse tensor arrays: how to provide online error checking for a range of structured sparsity levels while maintaining high utilization of the hardware. Experimental results highlight the minimum hardware overhead incurred by the proposed checking logic and its error detection properties after injecting random hardware faults on sparse tensor arrays that execute layers of ResNet50 CNN.

Error Checking for Sparse Systolic Tensor Arrays

General Matrix Multiplication (GEMM) is a computationally expensive operation that is used in many applications such as machine-learning. Hardware accelerators are increasingly popular for speeding up GEMM computation, with Tiled Matrix Multiplication (TMUL) in recent Intel processors being an example. Unfortunately, the TMUL hardware is susceptible to errors necessitating online error detection. Algorithm-based Error Detection techniques (ABED) is a powerful technique to detect errors in matrix multiplications. In this paper, we consider implementation of ABED that integrates seamlessly with the TMUL hardware to minimize performance overhead. Unfortunately, rounding errors introduced by floating-point operations do not allow a straightforward implementation of ABED in TMUL. Previously an error bound was considered for addressing rounding errors in ABED. If the error detection threshold is set too low, it will trigger false alarm while a loose bound will allow errors to escape detection. In this paper, we propose an adaptive error threshold that takes into account the TMUL input values to address the problem of false triggers and error escapes, and provide a taxonomy of various error classes. This threshold is obtained from theoretical error analysis but is not easy to implement in hardware. Consequently, we relax the threshold such that it can be easily computed in hardware. While ABED ensures error free computation it does not guarantee full coverage of all hardware faults. To address this problem, we propose an algorithmic pattern-generation technique to ensure full coverage for all hardware faults. To evaluate the benefits of our proposed solution, we conducted fault injection experiments and show that our approach does not produce any false alarms or detection escapes for observable errors. We conducted additional fault injection experiments on a Deep Neural Network (DNN) model and find that if a fault is not detected, it does not cause any misclassification.

Highly Efficient Self-Checking Matrix Multiplication on Tiled AMX Accelerators

This paper presents a two Nexys FPGAs implementation of a Least Significant Bit (LSB) watermarking applied on real-time speech signals over a serial communication system. The watermarking technique has been strengthened by means of a chaos-based encryption scheme for the used watermark image. The speech acquisition is performed using FPGA inbuilt microphone while the recovery has been realized through a loudspeaker as output device for the watermarked signal and VGA monitor for the watermark image respectively. The transmission of the watermarked signal has been implemented using Universal Asynchronous Receiver Transmitter (UART) serial protocol between two FPGA boards. The LSB IP-Cores developed and integrated in the watermarking prototype have been synthesized by means of a co-design approach using Vivado-HLS. The realized prototype has required performances of 1132 LUT area using a speed of 130 Mhz and a power consumption of no more than 159 mW. Lastly, good results have been obtained of watermarking imperceptibility and security with low robustness performances against signal processing and geometric cryptanalysis attacks.

General Matrix Multiplications (GEMMs) are widely used in scientific and machine learning applications. Convolutional Neural Networks (CNNs) rely primarily on convolution operation, which is often expressed as a GEMM problem. To speed up GEMM operations, modern CPUs include hardware accelerators specifically designed for this purpose. One such hard-ware accelerator is the Tile Multiplication unit (TMUL), which is supported by the Advanced Matrix Multiplication (AMX®) instruction set in the Intel Sapphire Rapids microarchitecture. However, like other frequently used hardware components, the TMUL is susceptible to permanent or persistent faults due to aging, which can lead to Silent Data Corruption (SDC). Google and Meta have recently reported recurring SDCs. Algorithm-based error detection (ABED) is a highly effective method for detecting persistent faults in GEMM operations. Our previous work involved a novel hardware implementation of ABED in TMUL, which could locate faults but only identify the of Fending matrix column, not the exact cell. In this paper, we present a self-repair technique for persistent faults in GEMM based on the aforementioned ABED approach. Our solution hinges on software-based column avoidance. When the hardware-based ABED detects an error caused by a faulty column in the TMUL, our software redirects computations to circumvent the faulty column. This eliminates the need for additional hardware modifications to ABED. We demonstrate that our proposed approach can perform self-repair for single faults for all matrix sizes, from those smaller than the TMUL dimension to larger matrices. Furthermore, we show that our solution can even correct multiple faults with low-performance overhead, and we report the performance overhead for multiple fault repair using a clustered fault model. Unlike prior solutions, our approach performs online detection and repair, enabling real-time correction of both persistent and intermittent faults.

A Novel Self-Repair Mechanism for Tiled Matrix Multiplication Unit

General Matrix Multiplication (GEMM) is instrumental in myriads of scientific, high-performance computing, and machine learning applications such as computer vision, recommendation models, and weather forecasts. It is vital to make them fail-safe in safety-critical and high-precision applications. Companies like Meta and Google have recently reported sporadic silent errors in GEMM computations traced to hardware sources. Silent errors are hard to detect, requiring specialized solutions to detect them. Hardware redundancy approaches such as double or triple modular redundancy effectively detect or correct such errors, but they have a large area and power overhead. Algorithm-based Fault Tolerance (ABFT) has been shown to offer an effective alternative at a far lower overhead. Modern CPUs feature advanced vector extensions (AVX) capable of executing SIMD instructions. This paper describes a new ABFT approach designed to take advantage of the AVX feature. Our core algorithm relies on the classical tile-based outer-product approach but enhances standard check-sum calculation using a tile vector. The implementation parameters are fine-tuned to fit the available number of AVX registers. Our results indicate that we can achieve 100% error detection in GEMM at an overhead of just 0.21% for the integer data type. Unfortunately, due to rounding errors, addition of floating-point numbers is not an associative operation, creating difficulties for ABFT. To mitigate the impact of rounding errors, we introduce the concept of relative error checking and perform error analysis for various error classes to show that the proposed approach totally eliminates false positive errors.

A Highly-Efficient Error Detection Technique for General Matrix Multiplication using Tiled Processing on SIMD Architecture

Digital information, being discrete in nature, possesses the capability to transfer more information at a faster rate with a significantly higher processing ease, all of which are in sharp contrast to analogue information. This has led to digital information being at the forefront of different types of media like image, video and audio. The only drawback of this has been the rise of copyright infringement issues, whereby the original owner becomes devoid of his claim over his uniquely designed creation because of duplicity and tampering by malicious users. Digital watermarking is a well sought out solution to this. The original user deliberately implants a distinctively identifiable impression onto the digital media for preventing copyright violation. The authors over here have focused on the specific domain of Medical Image Watermarking. Medical images like X-rays, USG, and MRI have revolutionized the medication fraternity by providing enhanced diagnosis and treatment of patients. But at the same time, copyright infringement of the medical images is a growing concern. To curb this problem, a notion of creating a binary masked image in comparison to the original medical image has been suggested. The mask helps in specifically identifying the region of interest (ROI)wherein the encrypted watermark has to be implanted for better imperceptibility and security. The encrypted watermark is embedded in the spatial domain, that is, the Least Significant Bit (LSB)of image pixels are modified in accordance to the watermarking bits. For a widespread acceptance of the proposed technique, the embedding and extracting methodologies have been implemented using Field Programmable Gate Array (FPGA). The imperceptibility, security and bit hiding capacity results are appreciably substantial. Further, a comparison of the suggested technique against some already relevant cutting edge techniques guarantees the superiority of the proposed technique.

FPGA Realization of Medical Image Watermarking

General matrix multiplication (GEMM) is common to many scientific and machine-learning applications. Convolution, the dominant computation in Convolutional Neural Networks (CNNs), can be formulated as a GEMM problem. Due to its widespread use, a new generation of processors features GEMM acceleration in hardware. Intel recently announced an Advanced Matrix Multiplication (AMX®) instruction set for GEMM, which is supported by 1kB AMX registers and a Tile Multiplication unit (TMUL) for multiplying tiles (sub-matrices) in hardware. Silent Data Corruption (SDC) is a well-known problem that occurs when hardware generates corrupt output. Google and Meta recently reported findings of SDC in GEMM in their data centers. Algorithm-Based Fault Tolerance (ABFT) is an efficient mechanism for detecting and correcting errors in GEMM, but classic ABFT solutions are not optimized for hardware acceleration. In this paper, we present a novel ABFT implementation directly on hardware. Though the exact implementation of Intel TMUL is not known, we propose two different TMUL architectures representing two design points in the area-power-performance spectrum and illustrate how ABFT can be directly incorporated into the TMUL hardware. This approach has two advantages: (i) an error can be concurrently detected at the tile level, which is an improvement over finding such errors only after performing the full matrix multiplication; and (ii) we further demonstrate that performing ABFT at the hardware level has no performance impact and only a small area, latency, and power overhead.

A Novel Fault-Tolerant Architecture for Tiled Matrix Multiplication

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A Highly-Efficient Error Detection Technique for General Matrix Multiplication using Tiled Processing on SIMD Architecture

FPGA Realization of Medical Image Watermarking

A Novel Fault-Tolerant Architecture for Tiled Matrix Multiplication