S. Wu
IBM
10 Papers
172 Citations
S. Wu is an academic researcher from IBM. The author has contributed to research in topics: CMOS & Silicon on insulator. The author has an hindex of 8, co-authored 10 publications.
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Papers
•Proceedings Article
Sub-25nm FinFET with advanced fin formation and short channel effect engineering
Tenko Yamashita,V. Basker,Theodorus E. Standaert,C.-C. Yeh,T. Yamamoto,Kingsuk Maitra,C.-H. Lin,J. Faltermeier,S. Kanakasabapathy,Miaomiao Wang,H. Sunamura,Hemanth Jagannathan,Alexander Reznicek,Stefan Schmitz,A. Inada,Junli Wang,H. Adhikari,N. Berliner,K-L. Lee,Pranita Kulkarni,Yu Zhu,Amit Kumar,A. Bryant,S. Wu,Thomas S. Kanarsky,Jin Cho,Erin Mclellan,S. Holmes,R. C. Johnson,T. Levin,James J. Demarest,James Chingwei Li,Philip J. Oldiges,John C. Arnold,Matt Colburn,Masami Hane,D. McHerron,Vamsi Paruchuri,Bruce B. Doris,R. J. Miller,Huiming Bu,Mukesh Khare,James A. O’Neill,Effendi Leobandung +43 more
- 14 Jun 2011
TL;DR: In this paper, a dual-work function gate-first process flow at 100 nm gate pitch and 40 nm fin pitch is demonstrated, achieving N/P Ion values of 1250/950 uA/m at 100nA/um at 1V, 1300/1000 uA /m with self-heating correction.
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A high performance 90nm SOI technology with 0.992 /spl mu/m 2 6T-SRAM cell
Mukesh Khare,S.H. Ku,Ricardo A. Donaton,Stephen E. Greco,Colin J. Brodsky,X. Chen,Anthony I. Chou,Ronald A. DellaGuardia,Sadanand V. Deshpande,Bruce B. Doris,S.K.H. Fung,Allen H. Gabor,Michael A. Gribelyuk,Steven J. Holmes,F. Jamin,W. Lai,Woo-Hyeong Lee,Yujun Li,P.A. McFarland,Renee T. Mo,Steven W. Mittl,Shreesh Narasimha,D. Nielsen,Robert J. Purtell,Werner A. Rausch,Sujatha Sankaran,J. Snare,Len Y. Tsou,A. Vayshenker,Tina Wagner,D. Wehella-Gamage,Ernest Y. Wu,S. Wu,W. Yan,E. Barth,Richard A. Ferguson,Percy V. Gilbert,Dominic J. Schepis,Akihisa Sekiguchi,Ronald D. Goldblatt,Jeffrey J. Welser,Karl Paul Muller,Paul D. Agnello +42 more
- 08 Dec 2002
TL;DR: In this paper, the smallest 6T SRAM cell reported to date with a cell area of 0.992 /spl mu/m/sup 2 was presented, which utilizes SiLK/spl trade/low-K dielectric material with a multilayer hard mask stack.
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A 0.25 /spl mu/m CMOS SOI technology and its application to 4 Mb SRAM
Dominic J. Schepis,Fariborz Assaderaghi,D.S. Yee,Werner A. Rausch,Atul C. Ajmera,Effendi Leobandung,Roy Childs Flaker,D. K. Sadana,Harold J. Hovel,T. Kebede,C. Schiller,S. Wu,Lawrence F. Wagner,M.J. Saccamango,Somnuk Ratanaphanyarat,M. Hsieh,Kurt A. Tallman,R.M. Martino,D. Fitzpatrick,M. Hakey,S.F. Chu,Bijan Davari,Ghavam G. Shahidi +22 more
- 07 Dec 1997
TL;DR: In this paper, a 0.25 /spl mu/m SOI CMOS is described, which uses undepleted SOI devices with nominal channel length of 0.15 /spl µ/m, minimum channel length in the 0.1 /spl μ/m range, supply voltage of 1.8 V, local interconnect, 6 levels of metal, and same ground rules as the comparable bulk 0.5 /spl mm/m CMOS.
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Scalability of SOI technology into 0.13 /spl mu/m 1.2 V CMOS generation
Effendi Leobandung,Melanie J. Sherony,Jeffrey W. Sleight,R. Bolam,Fariborz Assaderaghi,S. Wu,Dominic J. Schepis,Atul C. Ajmera,Werner A. Rausch,Bijan Davari,Ghavam G. Shahidi +10 more
- 06 Dec 1998
TL;DR: Based on ring oscillator performance, the 0.13 /spl mu/m SOI CMOS technology can achieve more than 25% faster speed and/or 50% less active power compared to a similar bulk technology.
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A high performance 0.13 /spl mu/m SOI CMOS technology with Cu interconnects and low-k BEOL dielectric
Peter Smeys,Vincent J. McGahay,I. Yang,James W. Adkisson,Klaus Dietrich Beyer,O. Bula,Z. Chen,B. Chu,J. Culp,S. Das,A. Eckert,L. Hadel,Michael J. Hargrove,Janet S. Herman,L. Lin,Randy W. Mann,Edward P. Maciejewski,Shreesh Narasimha,P. O'Neil,Stewart E. Rauch,Deborah A. Ryan,J. Toomey,L. Tsou,Patrick R. Varekamp,Richard A. Wachnik,T. Wagner,S. Wu,C. Yu,Paul D. Agnello,J. Connolly,S. Crowder,C. Davis,Richard A. Ferguson,Akihisa Sekiguchi,L. Su,Ronald D. Goldblatt,T.C. Chen +36 more
- 13 Jun 2000
TL;DR: In this paper, the authors describe a 1.2V high performance 0.13 /spl mu/m generation SOI technology using a tungsten damascene local interconnect.
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