S. Winters

TL;DR: In this article, the authors analyze the inaccuracies that occur in mismatch estimation methods that rely on combining measurements from a different die and wafers and use device arrays to overcome this limitation.

TL;DR: If effects of negative bias temperature instability in pMOS transistors are not adequately considered in NBTI characterization, assessment, benchmarking, and optimization, they could lead excessive expense in product reliability evaluation or, worse, to unanticipated, costly field reliability problems.

Abstract: To resolve performance yield issues it is required to detect and localize soft fails such as a contact having 500 ohms instead of its nominal 50 ohms. Soft fails can only be detected within very small test structures, which requires an array design to efficiently use the area of test chips. Here we present a novel high density test structure array, which will enable accurate 4 terminal measurements of 1000 or more very small devices under test (DUT) within each array. On average, only 2 selection devices are required per DUT, which will provide outstanding utilization of the test chip area. Experimental results reveal that within this array traditional test structures can be used beyond their intended purpose to detect additional defect types, which opens the door to significant reduction of overall mask and wafer consumption.

TL;DR: This paper will present methods how test structures can be redesigned to better support testing and modified test algorithms that will significantly reduce the test time by 50% and more, which will accelerate data analysis and increases efficient use of parametric test systems.