The system architecture and test results of the custom circuits and beam test system for the Multiplicity-Vertex Detector (MVD) for the PHENIX detector collaboration at the Relativistic Heavy Ion Collider (RHIC) are presented in this paper The final detector per-channel signal processing chain will consist of a preamplifier-gain stage, a current-mode summed multiplicity discriminator, a 64-deep analog memory (simultaneous read-write), a post-memory analog correlator, and a 10-bit 5 /spl mu/s ADC The Heap Manager provides all timing control, data buffering, and data formatting for a single 256-channel multi-chip module (MCM) Each chip set is partitioned into 32-channel sets Beam test (16-cell deep memory) performance for the various blocks will be presented as well as the ionizing radiation damage performance of the 12 /spl mu/m n-well CMOS process used for preamplifier fabrication

/pdf/design-and-performance-of-beam-test-electronics-for-the-4k2erx4fie.pdf

Design and performance of beam test electronics for the PHENIX Multiplicity Vertex Detector

A silicon microvertex detector (SMD) has been commissioned for the L3 experiment at the Large Electron-Positron colliding-beam accelerator (LEP) at CERN. The SMD is a 72,672 channel, two layer barrel tracker that is comprised of 96 ac-coupled, double-sided silicon detectors. Details of the design and construction are presented. >

/pdf/the-design-and-construction-of-a-double-sided-silicon-2rkp42xv01.pdf

The design and construction of a double-sided silicon microvertex detector for the L3 experiment at CERN

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The design and construction of a double-sided silicon microvertex detector for the L3 experiment at CERN