Metal-oxide-semiconductor field-effect transistors (MOSFETs) have shown impressive performance improvements over the past 10 years by incorporating strained silicon (Si) technology. This review gives an overview of the impact of strain on carrier mobility in Si n- and pMOSFETs by considering strain-induced band splitting, band warping and consequent carrier repopulation, and altered conductivity effective mass and scattering rate. Different surface orientations, channel directions, and gate electric fields are included for a fully theoretical understanding. The results are used to predict strain-enhanced silicon-on-insulator (SOI) and multigate device performance, mainly focusing on potential 22-nm and beyond device options such as double-gate and trigate fin field-effect transistor (FinFET) structures. Insights into strain-enhanced potential future channel materials (SiGe, Ge, and GaAs) are also summarized. Finally, recent technology nodes with strain engineering are reviewed, and the future developing t...

Strain: A Solution for Higher Carrier Mobility in Nanoscale MOSFETs

This paper describes a 60GHz LNA, implemented in a 65nm digital CMOS technology, that has a single-ended input and a differenntial output. At 59.3GHz, the LNA achieves a maximum voltage gain of 22.3dB (power gain of 19.3dB). The input matching is better than -lOdB over the entire 3dB bandwidth from 55.8GHz to 63.5GHz. The LNA has a minimum measured NF of 6.1dB, an output compression point of +2.7dBm and draws 29mA from a 1.2V supply.

A 22.3dB Voltage Gain 6.1dB NF 60GHz LNA in 65nm CMOS with Differential Output

Two injection-locked 2:1 frequency dividers for automotive radar applications achieve locking ranges from 82 to 94.1 GHz and from 34.3 to 42.1 GHz and consume 4mW and 8.4mW, respectively. The cascade of the two dividers can be locked from 79.7 to 81.6GHz. The 1mm2 chip is implemented in a 65nm CMOS process.

A 90GHz 65nm CMOS Injection-Locked Frequency Divider

Random microscopic fluctuations in the number and location of dopant atoms can cause a large variation in the threshold voltage (VT) of a MOS device. In this paper, we present a technique for fast characterization of random threshold voltage mismatch in MOS devices. Our VT scatter characterization method measures threshold voltage shift by monitoring the change in gate-to-source voltage VGS for a fixed drain current IDS and drain-to-source voltage VDS . We present circuit schematics to characterize VT scatter by measuring VGS variation for a large set of devices arranged in an individually addressable array. We report experimental results of VT scatter measurement from test chips fabricated in 65-nm silicon-on-insulator and 65-nm bulk CMOS processes. We also measure and report the magnitude of local device current mismatch caused by VT fluctuation.

Fast Characterization of Threshold Voltage Fluctuation in MOS Devices

The performance characteristics of transmission lines, silicon integrated waveguides, tunable LC resonators and passive combiners/splitters and baluns are described in this paper. It is shown that Q-factor for an on-chip LC tank peaks between 20 and 40 GHz in a 65 nm RF-CMOS technology; well below the bands proposed for many mm-wave applications. Simulations also predict that the Q-factor of differential CPW transmission lines on-chip can exceed 20 at 60 GHz in RF-CMOS when a floating shield is applied, outperforming unshielded variants employing more advanced metal stacks. A PA circuit demonstrator for advanced on-chip passive power combiners, splitters and baluns realizes peak-PAE of 18% and Psat better than 20 dBm into a 50 Ω load at 62 GHz. An outlook to the enablement of digitally intensive mm-wave ICs and low-loss passive interconnections (0.15 dB/mm measured loss at 100 GHz) concludes the paper.

Passive Circuit Technologies for mm-Wave Wireless Systems on Silicon

This paper presents a 65nm low power technology offering a dual gate oxide process, multiple Vt devices at a nominal operating voltage of 12V, a nine level hierarchical Cu interconnect back-end of line process with low k dielectrics and 0676mum2 and 054mum 2 SRAM cells, optimized for performance and density, respectively The key focus of this technology has been low cost, process simplicity and power reduction A gate dielectric with an nfet leakage current as low as 15pA/mum and with exceptional reliability characteristics has been demonstrated Moreover, competitive drive current has been achieved, 725/343muA/mum at an off current of 7nA/mum for n/pfets at nominal voltage A pfet performance enhancement of an additional 13% at 7nA/mum off current was achieved by using mobility enhancement techniques without adding process complexity An optimized NiSi process and high angle, low dose halo implants contribute to the reduced junction leakage and GIDL current

65nm cmos technology for low power applications

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65nm cmos technology for low power applications