A quantitative evaluation of the contributions of different sources of statistical variability, including the contribution from the polysilicon gate, is provided for a low-power bulk N-MOSFET corresponding to the 45-nm technology generation. This is based on a joint study including both experimental measurements and ldquoatomisticrdquo simulations on the same fully calibrated device. The position of the Fermi-level pinning in the polysilicon bandgap that takes place along grain boundaries was evaluated, and polysilicon-gate-granularity contribution was compared to the contributions of other variability sources. The simulation results indicate that random discrete dopants are still the dominant intrinsic source of statistical variability, while the role of polysilicon-gate granularity is highly dependent on Fermi-level pinning position and, consequently, on the structure of the polysilicon-gate material and its deposition and annealing conditions.

http://userweb.eng.gla.ac.uk/andrew.brown/papers/IEEE_EDL_2008_45nm.pdf

Quantitative Evaluation of Statistical Variability Sources in a 45-nm Technological Node LP N-MOSFET

Absorbing photonic crystals for silicon thin-film solar cells: Design, fabrication and experimental investigation

We present measurements for the standard deviation of the threshold voltage in n- and p-channel MOSFETs from the 45-nm low-power platform of STMicroelectronics. The measurements are compared with 3-D statistical simulations carried out with the Glasgow ldquoatomisticrdquo device simulator, considering random discrete dopants, line edge roughness, and the polysilicon granularity of the gate electrode. It was found that the surface potential pinning at the poly-Si grain boundaries (GBs), which is important for explaining the magnitude of the statistical variability of the n-channel MOSFETs, plays a negligible role in the p-channel case. First-principle simulation of low-angle silicon GBs is performed in order to explain the systematically observed differences in the threshold voltage standard deviation of the measured n- and p-channel MOSFETs.

http://userweb.eng.gla.ac.uk/andrew.brown/papers/IEEE_EDL_2008_Asymmetry.pdf

Origin of the Asymmetry in the Magnitude of the Statistical Variability of n- and p-Channel Poly-Si Gate Bulk MOSFETs

With the continuous scaling down of the critical dimensions (CDs) of semiconductor devices, the linewidth roughness (LWR) becomes a non-negligible parameter that needs to be controlled within 1nm (at 3σ) for the 32nm node and beyond. In this article, the authors have used a CD-atomic force microscopy to investigate the evolution of the LWR during the subsequent lithography and plasma etching steps involved in the patterning of polysilicon transistor gates. The authors demonstrate that the LWR present on the etching mask [photoresist/bottom antireflective coating (BARC), SiO2 or amorphous carbon hard masks] right before the gate etching is transferred into the polysilicon during the HBr∕Cl2∕O2 gate etching step. Thus, the final polysilicon LWR directly is strongly dependent on the lithography and plasma etching steps preceding the gate etching step. The authors show that by applying plasma treatment to minimize the resist mask LWR prior to all the other etching steps or by optimizing the BARC opening plasm...

Linewidth roughness transfer measured by critical dimension atomic force microscopy during plasma patterning of polysilicon gate transistors

Line edge roughness (LER) has been identified as a potential source of uncertainty in optical scatterometry measurements. Characterizing the effect of LER on optical scatterometry signals is required to assess the uncertainty of the measurement. However, rigorous approaches to modeling the structures that are needed to simulate LER can be computationally expensive. In this work, we compare the effect of LER on scatterometry signals computed using an effective medium approximation (EMA) to those computed with realizations of rough interfaces. We find that for correlation lengths much less than the wavelength but greater than the rms roughness, an anisotropic EMA provides a satisfactory approximation in the cases studied.

/pdf/effective-medium-approximations-for-modeling-optical-2i025cpmzs.pdf

Effective medium approximations for modeling optical reflectance from gratings with rough edges.

As critical dimensions (CD) for semiconductor devices shrink to a few tens of nanometers, the line edge roughness (LER) and linewidth roughness (LWR) becomes a critical issue. For this study, we used a new 3D CD-AFM which enables us to characterize LER and LWR along the features after each technological step of standard gate patterning processes. Isolated lines with CDs going from 20nm and 100nm were written with an e-beam lithography tool. First, we transfer the resist mask into silicon to determine the influence of different plasma chemistries on LER. Then, the resist mask is transferred into a standard CMOS gate stack: SiO2 hard mask, polysilicon, dielectric gate. The results after e-beam lithography show that the LWR measured at the bottom of the pattern is higher than the one measured at the middle. It can be attributed to the effect of backscattered electrons. Then, we show that for smaller dimensions, the trimming that occurs during the hard mask opening process weakens the resist and increases dra...

Line edge roughness characterization with a three-dimensional atomic force microscope: Transfer during gate patterning processes

Hybrid lithography process for nano-scale devices

Low molecular weight negative tone chemically amplified resist has been exposed with 100kV electron beam writer with a postexposure bake temperature varying between 85 and 100°C. Isolated lines, with feature size ranging from 20 up to 100nm, have been characterized with scanning electron microscopy and critical dimension atomic force microscopy. A simple kinetic reaction law and lateral acid diffusion into the resist layer were taken into account for the cross-linking reaction simulation. Top view and full three-dimensional measurements of resist feature have been fitted with an analytical expression. A cost function was introduced to extract the reaction order (m) and the acid diffusion coefficient (D) of the second Fick’s law. Whatever the process temperature used, a constant value for m(m=2.6) was found, and D was found to vary from 2to45nm2∕s for a postexposure bake temperature of 85 and 100°C, respectively. Depending on the metrology technology used for resist characterization resist parameter extrac...

Full three-dimensional characterization of 25nm lines for chemically amplified resist simulation

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Papers

Line edge roughness characterization with a three-dimensional atomic force microscope: Transfer during gate patterning processes

Hybrid lithography process for nano-scale devices

Full three-dimensional characterization of 25nm lines for chemically amplified resist simulation