S. Minehane
PDF Solutions
12 Papers
131 Citations
S. Minehane is an academic researcher from PDF Solutions. The author has contributed to research in topics: CMOS & Negative-bias temperature instability. The author has an hindex of 8, co-authored 12 publications.
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Papers
Dynamic recovery of negative bias temperature instability in p-type metal–oxide–semiconductor field-effect transistors
M. Ershov,Sharad Saxena,H. Karbasi,S. Winters,S. Minehane,J. Babcock,R. Lindley,Paul A. Clifton,M. Redford,A. Shibkov +9 more
TL;DR: In this paper, an unexpected physical phenomenon called dynamic recovery of negative bias temperature instability (NBTI) is reported, which includes a very fast transient (seconds time scale) followed by a slow (tens of minutes) transient, which tends to saturate.
180
Variation in Transistor Performance and Leakage in Nanometer-Scale Technologies
Sharad Saxena,Christopher Hess,H. Karbasi,Angelo Rossoni,Stefano Tonello,P. McNamara,S. Lucherini,S. Minehane,Christoph Dolainsky,M. Quarantelli +9 more
TL;DR: In this paper, an infrastructure for characterizing the various types of variation in transistor characteristics is described, and a sample of results obtained from applying this infrastructure to a number of technologies at the 90-, 65-, and 45-nm nodes is presented.
126
Application-specific worst case corners using response surfaces and statistical models
TL;DR: A new statistical methodology to determine the worst-case corners for a set of circuit performances using the novel concept of relaxation coefficient to ensure that the corners capture the min/max values of all the circuit performances at the desired statistical level is presented.
82
Application specific worst case corners using response surfaces and statistical models
M. Sengupta,Sharad Saxena,L. Daldoss,G. Kramer,S. Minehane,Jianjun Cheng +5 more
- 22 Mar 2004
TL;DR: A new statistical methodology to determine the worst case corners for a set of circuit performances with the novel concept of a relaxation coefficient to ensure that the corners capture the minimum/maximum values of all the circuit performances at the desired tolerance level.
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Characterization and modeling of MOSFET mismatch of a deep submicron technology
M. Quarantelli,Sharad Saxena,Nicola Dragone,J. Babcock,Christopher Hess,S. Minehane,S. Winters,Jianjun Chen,H. Karbasi,Carlo Guardiani +9 more
- 17 Mar 2003
TL;DR: In this article, the authors analyze the inaccuracies that occur in mismatch estimation methods that rely on combining measurements from a different die and wafers and use device arrays to overcome this limitation.
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