S. Manikandan
Thiagarajar College of Engineering
13 Papers
26 Citations
S. Manikandan is an academic researcher from Thiagarajar College of Engineering. The author has contributed to research in topics: Threshold voltage & Scaling. The author has an hindex of 4, co-authored 12 publications. Previous affiliations of S. Manikandan include Kalasalingam University.
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Papers
Android Application based Smart Bus Transportation System for Pandemic Situations
R. Santhana Krishnan,S. Manikandan,J. Relin Francis Raj,K. Lakshmi Narayanan,Y. Harold Robinson +4 more
- 04 Feb 2021
TL;DR: In this article, a new Android Application based Smart Bus Transportation System was introduced which guides the passengers in booking the bus tickets using the Android Application and also helps the passengers to keep an update on bus location based on their request This system also sends alert message few minutes in advance to the passengers before the bus reaches the passengers boarding point.
19
Impact of uniform and non-uniform doping variations for ultrathin body junctionless FinFETs
TL;DR: In this article, the impact of Fin width (Fw), Fin height (Fh), Channel length (Lg) and Gate Oxide (tox) on drain current, ION/IOFF ratio, subthreshold swing, Drain Induced Barrier Lowering (DIBL) of Si-based Bulk Junctionless FinFETs is investigated.
19
Analytical Model of Double Gate Stacked Oxide Junctionless Transistor Considering Source/Drain Depletion Effects for CMOS Low Power Applications
TL;DR: In this article, a 2D analytical model for double gate junctionless transistors with a SiO2/HfO2 stacked oxide structure is proposed, and the model is solved by Poisson's equation using the variable separation method.
18
Analytical Modeling of Dual Material Gate All around Stack Architecture of Tunnel FET
N. B. Balamurugan,G. Lakshmi Priya,S. Manikandan,G. Srimathi +3 more
- 04 Jan 2016
TL;DR: An analytical model has been proposed to study the behavior of Dual Material Gate All Around Stack Architecture of TFET (DMGAASA TFET) in suppressing short channel effects and the analytical results obtained agree well with the simulated results obtained from TCAD sentaurus device simulator.
13
A Compact Analytical Model for 2D Triple Material Surrounding Gate Nanowire Tunnel Field Effect Transistors
TL;DR: In this article, a 2D analytical model for surface potential and electric field of a p-type tri-material gate (TMG) gate-all-around (GAA) nanowire tunneling field effect transistor (TFET) was proposed.
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