S. Ghosh
1 Papers
S. Ghosh is an academic researcher. The author has contributed to research in topics: Electrical efficiency & Integrated injection logic. The author has co-authored 1 publications.
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Papers
A 2GHz, 7W (max) 64b Power TM Microprocessor Core
D. Murray,J. Burnette,Brian J. Campbell,M. Chung,B. Fernandes,S. Ghosh,Rajat Goel,G. Hess,Hang Huang,Zhibin Huang,N. Javarappa,P. Kanapathipillai,F. Klass,Fang Liu,A. Mehta,Y. Modukuru,N. Nerurkar,A. Radhakrishnan,S. Santhanam,Junji Sugisawa,S. Sundar,H.J. Tarn,R. Wen,E. Wu,Jung-Cheng Yeh,J. Yong,S. Zambare +26 more
- 01 Sep 2007
TL;DR: The PA6T core is an out-of-order superscalar implementation of the power architecture that achieves power efficiency through micro-architecture, logic, and circuit optimizations.