Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logical, and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.

/pdf/power-minimization-in-ic-design-principles-and-applications-4l53tahw7t.pdf

Power minimization in IC design: principles and applications

Power consumption is rapidly becoming an area of growing concern in IC and system design houses. Issues such as battery life, thermal limits, packaging constraints and cooling options are becoming key factors in the success of a product. As a consequence, IC and system designers are beginning to see the impact of power on design area, design speed, design complexity and manufacturing cost. While process and voltage scaling can achieve significant power reductions, these are expensive strategies that require industry momentum, that only pay off in the long run. Technology independent gains for power come from the area of design for low power which has a much higher return on investment (ROI). But low power design is not only a new area but is also a complex endeavour requiring a broad range of synergistic capabilities from architecture/microarchitecture design to package design. It changes traditional IC design from a two-dimensional problem (Area/performance) to a three-dimensional one (Area/Performance/Power). This paper describes the CAD tools and methodologies required to effect efficient design for low power. It is targeted to a wide audience and tries to convey an understanding of the breadth of the problem. It explains the state of the art in CAD tools and methodologies. The paper is written in the form of a tutorial, making it easy to read by keeping the technical depth to a minimum while supplying a wealth of technical references. Simultaneously the paper identifies unresolved problems in an attempt to incite research in these areas. Finally an attempt is made to provide commercial CAD tool vendors with an understanding of the needs and time frames for new CAD tools supporting low power design. >

/pdf/power-conscious-cad-tools-and-methodologies-a-perspective-5f06ec9yt2.pdf

Power conscious CAD tools and methodologies: a perspective

In this paper we address the growing issue of gate oxide leakage current (I/sub gate/) at the circuit level. Specifically, we develop a fast approach to analyze the total leakage power of a large circuit block, considering both I/sub gate/ and subthreshold leakage (I/sub sub/). The interaction between I/sub sub/ and I/sub gate/ complicates analysis in arbitrary CMOS topologies and we propose simple and accurate heuristics based on lookup tables to quickly estimate the state-dependent total leakage current for arbitrary circuit topologies. We apply this method to a number of benchmark circuits using a projected 100-nm technology and demonstrate accuracy within 0.09% of SPICE on average with a four order of magnitude speedup. We then make several observations on the impact of I/sub gate/ in designs that are standby power limited, including the role of device ordering within a stack and the differing state dependencies for NOR versus NAND topologies. Based on these observations, we propose the use of pin reordering as a means to reduce I/sub gate/. We find that for technologies with appreciable I/sub gate/, this technique is more effective at reducing total leakage current in standby mode than state assignment, which is often used for I/sub sub/ reduction.

/pdf/gate-oxide-leakage-current-analysis-and-reduction-for-vlsi-32fxe0e1wo.pdf

Gate oxide leakage current analysis and reduction for VLSI circuits

We present a new approach for estimation and optimization of the average stand-by power dissipation in large MOS digital circuits. To overcome the complexity of state dependence in average leakage estimation, we introduce the concept of "dominant leakage states" and use state probabilities. Our method achieves speed-ups of 3 to 4 orders of magnitude over exhaustive SPICE simulations while maintaining accuracies within 9% of SPICE. This accurate estimation is used in a new sensitivity-based leakage and performance optimization approach for circuits using dual V/sub t/ processes. In tests on a variety of industrial circuits, this approach was able to obtain 81-100% of the performance achievable with all low V/sub t/ transistors, but with 1/3 to 1/6 the stand-by current.

/pdf/stand-by-power-minimization-through-simultaneous-threshold-2xsgi0j3ta.pdf

Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing

A system developed to synthesize both finite state machines and combinational logic for low-power applications, called SYCLOP, is described. SYCLOP tries to minimize the transition density at the internal nodes of a circuit to minimize power dissipation during normal operation. As input signal probabilities and transition densities are considered during the synthesis process, a particular circuit can be synthesized in different ways for different applications that require different types of inputs. For the present state inputs to the combinational circuit of a state machine, simulation was used to determine the signal probabilities and transition densities. The algorithm is not limited by the number of bits used for state assignment. The multilevel optimization process extracts kernels so that there is a balance between area and power optimization. Results have been obtained for a wide range of MCNC benchmark examples. >

Circuit activity based logic synthesis for low power reliable operations

Two methods for the calculation of node signal probabilities in combinational networks are presented. These techniques provide a better accuracy than existing algorithms and a deeper insight in the effects of first-order correlations due to multiple fan-out reconvergences. The proposed algorithms are shown to compare favorably with existing procedures in the analysis of significant benchmarks, both in accuracy and in computational efficiency. >

Estimate of signal probability in combinational logic networks

An investigation of the properties of multiple input shift registers for signature analysis is presented. The assumption of independent errors at the register inputs has been used to model the register behavior as a Markov process whose equations have been solved to obtain the exact dependence of aliasing probabilities as a function of test length, input error probabilities, and feedback structure. Some unique featured of maximum-length registers are proven. Accurate simplified expressions of aliasing probability are derived for use as tools in the evaluation of the coverage. >

Aliasing in signature analysis testing with multiple input shift registers

Signature analysis with multiple-input shift registers (MISRs) is often used to realize efficient built-in self-test of digital VLSI circuits. The authors present a statistical theory that explains the dependence of aliasing probability on the main MISR features, such as length and feedback network, and thus makes it possible to prove criteria for the MISR design. The assumption of independent errors at the register inputs is used to model the register behavior as a Markov process, whose equations are then solved to obtain the exact dependence of aliasing probability as a function of test length, input error probabilities, and feedback structure. >

Aliasing in signature analysis testing with multiple-input shift-registers

Two methods for the calculation of fault detection probabilities in combinational networks are presented. These methods provide a better accuracy than existing algorithms and a deeper insight into the effects of first order correlations to multiple fan-out reconvergencies. These techniques have been applied to standard benchmarks as well as to a few commercial circuits and have shown to provide a significant improvement compared with existing methods with minimal drawbacks in terms of required computing resources. >

Improved testability evaluations in combinational logic networks

A novel method to obtain weights for weighted pseudorandom built-in self-test (BIST) techniques that can be used to solve the fault coverage problems posed by hard-to-detect faults is presented. In the method, weights are directly obtained by means of the stuck-at fault simulation instead of using testability measures. In this way, a single set of weights is obtained that is more conveniently implemented than the multiple distributions provided by alternative techniques. Results obtained on benchmark circuits show a large increase of the achieved fault coverage values compared with the case of uniformly biased pseudorandom sequences. >

http://ieeexplore.ieee.org/iel2/335/6520/00257451.pdf

Weighted pseudorandom generation for built-in self-test

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