This paper reviews the history of strained-silicon and the adoption of uniaxial-process-induced strain in nearly all high-performance 90-, 65-, and 45-nm logic technologies to date. A more complete data set of n- and p-channel MOSFET piezoresistance and strain-altered gate tunneling is presented along with new insight into the physical mechanisms responsible for hole mobility enhancement. Strained-Si hole mobility data are analyzed using six band k/spl middot/p calculations for stresses of technological importance: uniaxial longitudinal compressive and biaxial stress on [001] and [110] wafers. The calculations and experimental data show that low in-plane and large out-of-plane conductivity effective masses and a high density of states in the top band are all important for large hole mobility enhancement. This work suggests longitudinal compressive stress on [001] or [110] wafers and channel direction offers the most favorable band structure for holes. The maximum Si inversion-layer hole mobility enhancement is estimated to be /spl sim/ 4 times higher for uniaxial stress on (100) wafer and /spl sim/ 2 times higher for biaxial stress on (100) wafer and for uniaxial stress on a [110] wafer.

Uniaxial-process-induced strained-Si: extending the CMOS roadmap

Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator substrates have been demonstrated down to 15-nm gate lengths. We have also introduced the FinFET, a double-gate device structure that is relatively simple to fabricate and can be scaled to gate lengths below 10 nm. In this paper, some of the key elements of these technologies are described, including sublithographic patterning, the effects of crystal orientation and roughness on carrier mobility, gate work function engineering, circuit performance, and sensitivity to process-induced variations.

Extremely scaled silicon nano-CMOS devices

Strain engineering using lattice-mismatched S/D in transistors and their combination with other stressors and optimum surface/channel orientations is very attractive and important for the continued improvement of CMOS performance in addition to device scaling

https://iopscience.iop.org/article/10.1088/0268-1242/22/1/S42/pdf

Enhancing CMOS Transistor Performance Using Lattice-Mismatched Materials in Source/Drain Regions

In this letter, the physical and electrical properties of physical vapor deposited (PVD) hafnium nitride (HfN) is studied for the first time as the metal gate electrode for advanced MOS devices applications. It is found that HfN possesses a midgap work function in tantalum nitride (TaN)/HfN/SiO/sub 2//Si MOS structures. TaN/HfN stacked metal-gated MOS capacitors exhibit negligible variations on equivalent oxide thickness (EOT), leakage current, and work function upon high-temperature treatments (up to 1000 /spl deg/C), demonstrating the excellent thermal stability of HfN metal gate on SiO/sub 2/. Our results suggest that HfN metal electrode is an ideal candidate for the fully depleted SOI and/or symmetric double gate MOS devices application.

Physical and electrical characteristics of HfN gate electrode for advanced MOS devices

This article is targeted as an introduction to the physics of strained Si and the current state of the art in uniaxial strained Si MOSFET. The first part of the article explains how strain alters the valence and conduction band of Si as well as scattering rates. This is followed by a review of state-of-the-art strained techniques being implemented in 90- and 65-nm process technologies. Finally, we conclude with a discussion of the future scalability of strained Si MOSFETs in the ballistic regime and nanoscale CMOS.

http://ieeexplore.ieee.org/iel5/101/32496/01517386.pdf

Mobility enhancement

We report for the first time PMOS drive current enhancement with in-situ boron doped SiGe incorporation in recessed S/D regions for devices built on thin body SOI substrate. For P-channel PD-SOI devices with 450 A silicon on insulator and 38nm gate length, 35% linear drain current enhancement and 20% saturation drain current improvement have been achieved with this approach. Device integration and performance improvement are discussed below.

Embedded SiGe S/D PMOS on thin body SOI substrate with drive current enhancement

We report for the first time electrical characterization of HfO 2 p- and n-MOSFETs with CVD TiN and PVD TaSiN gates respectively fabricated using conventional CMOS integration. Their performance is compared to PVD TiN-gated HfO 2 and SiO 2 n- and p-MOSFETs. To understand the issues with metal gates on high K gate dielectrics, PVD TiN MOSFETs were extensively characterized. At 10nA/μm leakage, 0.345mA/μm drive current was obtained from PVD TiN/HfO 2 p-MOSFETs. HfO 2 n-MOSFETs with metal gates show about 10 4 times reduction in gate leakage compared to poly/SiO 2 devices.

Metal gate MOSFETs with HfO2 gate dielectric

We report for the first time electrical characterization of HfO/sub 2/ p- and n-MOSFETs with CVD TiN and PVD TaSiN gates respectively fabricated using conventional CMOS integration. Their performance is compared to PVD TiN-gated HfO/sub 2/ and SiO/sub 2/ n- and p-MOSFETs. To understand the issues with metal gates on high K gate dielectrics, PVD TiN MOSFETs were extensively characterized. At 10 nA//spl mu/m leakage, 0.345 mA//spl mu/m drive current was obtained from PVD TiN/HfO/sub 2/ p-MOSFETs. HfO/sub 2/ n-MOSFETs with metal gates show about 10/sup 4/ times reduction in gate leakage compared to poly/SiO/sub 2/ devices.

Metal gate MOSFETs with HfO/sub 2/ gate dielectric

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Embedded SiGe S/D PMOS on thin body SOI substrate with drive current enhancement

Metal gate MOSFETs with HfO2 gate dielectric

Metal gate MOSFETs with HfO/sub 2/ gate dielectric