This paper describes the design of a programmable parallel architecture that is to be used for signal pre-processing in intelligent embedded vision systems. The architecture has been implemented and tested using a Celoxica RC1000 prototyping platform with a Xilinx XCY2000E FPGA. The system operates at a clock rate of 50 MHz and can perform pre-processing functions such as filtering, correlation and transformation on an image of 256x256 pixels at up to 667 frames/s.

An FPGA implementation of a flexible, parallel image processing architecture suitable for embedded vision systems

New generations of automobiles will include driver assistance systems requiring powerful, low-cost processors to handle video/camera applications and to enable fast, convenient application development. Shrinking feature sizes on processors already in development will bring substantial increases in system speed and functionality.

A 100-GOPS programmable processor for vehicle vision systems

To follow rapid evolution of media processing algorithms, the latest media processing architecture enhances the execution efficiencies of media applications by adding a programmable vision processor and by improving memory hierarchy, while complicates the programming. In this paper, the features of this architecture are analyzed, the reason of inefficiency of media application implemented by general programming model is studied and SPUR programming model is proposed. In SPUR, media data and operations are expressed as media streams and corresponding operations naturally. Moreover, algorithm is divided into high-level part written by SP-C and low-level part written by UR-C. Fine-grained data parallelism are exploited explicitly as well. Experimental results show that SPUR provides programmer a novel, expressive and efficient programming way, and obviously improves readability, robustness, development efficiency and object-code quality of media applications.

A programming model for an embedded media processing architecture

Vision is expected to play important roles for car safety enhancement. Imaging systems can be used to enlarging the vision field of the driver. For instance capturing and displaying views of hidden areas around the car which the driver can analyze for safer decision-making. Vision systems go a step further. They can autonomously analyze the visual information, identify dangerous situations and prompt the delivery of warning signals. For instance in case of road lane departure, if an overtaking car is in the blind spot, if an object is approaching within collision course, etc. Processing capabilities are also needed for applications viewing the car interior such as "intelligent airbag systems" that base deployment decisions on passenger features. On-line processing of visual information for car safety involves multiple sensors and views, huge amount of data per view and large frame rates. The associated computational load may be prohibitive for conventional processing architectures. Dedicated systems with embedded local processing capabilities may be needed to confront the challenges. This paper describes a dedicated sensory-processing architecture for collision warning which is inspired by insect vision. Particularly, the paper relies on the exploitation of the knowledge about the behavior of Locusta Migra- toria to develop dedicated chips and systems which are integrated into model cars as well as into a commercial car (Volvo XC90) and tested to deliver collision warnings in real traffic scenarios.

/pdf/insect-vision-inspired-collision-warning-vision-processor-4rbkaex815.pdf

Insect-vision inspired collision warning vision processor for automobiles

This paper presents a programmable multiprocessor architecture suitable for image preprocessing in embedded vision systems. The architecture is made up of sixteen 16-bit input/32-bit output parallel processing elements, connected to an intelligent DMA channel and frame buffers. Each element of the SIMD processing array can be programmed using a RISC-like instruction set, and is capable of performing DSP operations commonly used in image preprocessing algorithms. The architecture has been prototyped on an FPGA connected to a 256/spl times/256-pixel CMOS sensor, achieving 3.23 GOPS and up to 667 FPS of throughput at a clock frequency of 50 MHz. It is estimated to achieve a minimum of 6.46 GOPS and 1334 FPS at a clock frequency of 100 MHz when implemented in VLSI.

A programmable image signal processing architecture for embedded vision systems

whereas virtual round-table conferencing needs at the sender’s side to find a person’s head, cut it from the background, code it and at the receiver’s side to decode and insert it at the round-table by means of geometric transformations (figure below shows virtual round table) Hence, a vision processor has to support image processing, coding/decoding and 3D graphics Accordingly, a representative body of algorithms from these 3 vision fields was analysed with respect to computational power, elementary instructions and data types needed It was found that scalar, vector and matrix constitute the main data types, and a set of 205 visionbased instructions for vector and matrix types was defined Architectural studies led to a parallel array of 16 processing elements (PE) executing the vision instructions on vector and matrix data, as well as to special cache architectures adapted to the new data types For decoding of instructions, a set of controllers had to be introduced that would deliver control bits to the amount of what full-fledged general-purpose processors use to generate, but at a decade lower power level Finally, starting off from the OAK DSP and its Ccompiler, a programming model extending C by some vision based semantics, but keeping the C syntax was thought to be adequate for the user It is the set of 205 application-specific instructions and its computing and memory architecture that make the vision processor a generic one (see [1] for recent alternatives) In the following, only the functional highlights are reported

A 53-GOPS programmable vision processor for processing, coding-decoding and synthesizing of images

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A 53-GOPS programmable vision processor for processing, coding-decoding and synthesizing of images