With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage1. This led to a fundamental change in the gate stack in 2008, the incorporation of high-dielectric-constant HfO2 (ref. 2), which remains the material of choice to date. Here we report HfO2-ZrO2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric-antiferroelectric order, directly integrated onto Si transistors, and scaled down to approximately 20 ångströms, the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal-oxide-semiconductor capacitors is equivalent to an effective SiO2 thickness of approximately 6.5 ångströms. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO2-based high-dielectric-constant gate stacks without scavenging the interfacial SiO2, which has adverse effects on the electron transport and gate leakage current3. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. This work demonstrates that ultrathin ferroic HfO2-ZrO2 multilayers, stabilized with competing ferroelectric-antiferroelectric order in the two-nanometre-thickness regime, provide a path towards advanced gate oxide stacks in electronic devices beyond conventional HfO2-based high-dielectric-constant materials. 

/pdf/ultrathin-ferroic-hfo2-zro2-superlattice-gate-stack-for-2kg1dzup.pdf

Ultrathin ferroic HfO2–ZrO2 superlattice gate stack for advanced transistors

This paper highlights the intrinsic reliability capabilities of Intel's 22nm process technology, which introduced the tri-gate transistor architecture and features a 3rd generation high-κ/metal-gate process. Results are detailed from all traditional transistor reliability mechanisms, including BTI, TDDB, SILC, and HCI. In addition, characteristics unique to this transistor architecture and process technology are described.

Intrinsic transistor reliability improvements from 22nm tri-gate technology

In this paper, we carried out a systematic investigation on gate degradation and the physical mechanism of the Schottky-type ${p}$ -GaN gate HEMTs under positive gate voltage stress. The frequency- and temperature-dependent measurements have been conducted. It is found that the time-dependent gate degradation exhibits weak relevance with frequencies ranging from 10 to 100 kHz under dynamic gate stress and is similar to that in static gate stress. Both the gate breakdown voltage (BV) and mean-time-to-failure (MTTF) show positive temperature dependence. Moreover, the current–voltage ( I–V ) characteristics and threshold voltage ( ${V}_{\text {TH}}$ ) instability of ${p}$ -GaN devices before/after gate degradation are compared and analyzed. The degraded Schottky junction exhibits an ohmic-like gate behavior. It is revealed that under a large gate bias stress, high-energy electrons accelerated in the depletion region of the ${p}$ -GaN layer would promote the formation of defect levels near the metal/ ${p}$ -GaN interface, leading to the initial ${p}$ -GaN layer degradation. The subsequent high gate leakage density could cause the final degradation of the AlGaN barrier.

Frequency- and Temperature-Dependent Gate Reliability of Schottky-Type ${p}$ -GaN Gate HEMTs

A comprehensive modeling framework is presented to predict the time kinetics of negative bias temperature instability stress and recovery during and after dc and ac stresses and also during mixed dc–ac stress. The model uses uncorrelated contributions from the generation of interface and bulk traps and hole trapping in preexisting bulk traps. Ultrafast measured data at different stresses and recovery biases, temperature, duty cycle and frequency, as well as arbitrary time segments with dynamically varying voltage, frequency, and activity are predicted. The role of nitrogen in the gate insulator is explained. End-of-life degradation is determined under dc and ac use conditions.

BTI Analysis Tool—Modeling of NBTI DC, AC Stress and Recovery Time Kinetics, Nitrogen Impact, and EOL Estimation

The impact of self-heating effect (SHE) on device reliability characterization, such as BTI, HCI, and TDDB, is extensively examined in this work. Self-heating effect and its impact on device level reliability mechanisms is carefully studied, and an empirical model for layout dependent SHE is established. Since the recovery effect during NBTI characterization is found sensitive to self-heating, either changing V
 T
 shift as index or adopting μs-delay measurement system is proposed to get rid of SHE influence. In common HCI stress condition, the high drain stress bias usually leads to high power or self-heating, which may dramatically under-estimate the lifetime extracted. The stress condition V
 g
 = 0.6~0.8V
 d
 is suggested to meet the reasonable operation power and self-heating induced temperature rising. Similarly, drain-bias dependent TDDB characteristics are also under-estimated due to the existence of SHE and need careful calibration to project the lifetime at common usage bias.

Self-heating effect in FinFETs and its impact on devices reliability characterization

High-K (HK) and Metal-Gate (MG) transistor reliability is very challenging both from the standpoint of introduction of new materials and requirement of higher field of operation for higher performance. In this paper, key and unique HK+MG intrinsic transistor reliability mechanisms observed on 32nm logic technology generation is presented. We'll present intrinsic reliability similar to or better than 45nm generation.

Reliability characterization of 32nm high-K and Metal-Gate logic transistor technology

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Reliability characterization of 32nm high-K and Metal-Gate logic transistor technology