Sensor networks are long-running computer systems with many sensing/compute nodes working to gather information about their environment, process and fuse that information, and in some cases, actuate control mechanisms in response. Like traditional parallel systems, communication between nodes is of fundamental importance, but is typically accomplished via wireless transceivers. One further key attribute of sensor networks is that they are almost always long running systems, intended to operate in situ, with minimal direct human intervention, for months or years. This requirement for long-running autonomy mandates careful design of the runtime system that manages applications on each node, to ensure reliability and ease of upgrades over the life of the system.This paper describes Impala, a middleware architecture that enables application modularity, adaptivity, and repair-ability in wireless sensor networks. Impala allows software updates to be received via the node's wireless transceiver and to be applied to the running system dynamically. In addition, Impala also provides an interface for on-the-fly application adaptation in order to improve the performance, energy-efficiency, and reliability of the software system. Impala has been designed to be a part of the ZebraNet mobile sensor network, but we are also prototyping it within HP/Compaq iPAQ Pocket PC handhelds. We present performance data for both real system measurements of the Pocket PC version as well as simulations of a full mobile sensor system deployment. Overall, Impala is a lightweight runtime system that can greatly improve system reliability, performance, and energy-efficiency. The ideas introduced here for sensor networks have applicability more broadly in other long-running autonomous parallel systems as well.

/pdf/impala-a-middleware-system-for-managing-autonomic-parallel-4qpzx2a6le.pdf

Impala: a middleware system for managing autonomic, parallel sensor systems

In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.

Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like)

A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock rate is disclosed, wherein the first clock rate is higher than the second and wherein the coarse grained logic elements comprise storage means for storing data needed to be processed.

Data processing device and method

Data processing method and device

The wireless sensor network (WSN) is an interesting area for modern day research groups. Tiny sensor nodes are deployed in a diversity of environments but with limited resources. Scarce resources compel researchers to employ an operating system that requires limited memory and minimum power. Tiny operating system (TinyOS) is a widely used operating system for sensor nodes, which provides concurrency and flexibility while adhering to the constraints of scarce resources. Comparatively, TinyOS is considered to be the most robust, innovative, energy-efficient, and widely used operating system in sensor networks. This paper looks at the state-of-the-art TinyOS and the different dimensions of its design paradigm, programming model, execution model, scheduling algorithms, concurrency, memory management, hardware support platforms, and other features. The addition of different features in TinyOS makes it the operating system of choice for WSNs. Sensing nodes with TinyOS seem to show more flexibility in supporting diverse types of sensing applications.

TinyOS-New Trends, Comparative Views, and Supported Sensing Applications: A Review

We have integrated an image processing system built around PADDI-2, a custom 48 node MIMD parallel DSP. The system includes image processing algorithms, a graphical SFG tool, a simulator, routing tools, compilers, hardware configuration and debugging tools, application development libraries, and software implementations for hardware verification. The system board, connected to a SPARCstation via a custom Sbus controller, contains 384 processors in 8 VLSI chips. The software environment supports a multiprocessor system under development (VGI-1). The software tools and libraries are modular, with implementation dependencies isolated in layered encapsulations.

/pdf/a-multiprocessor-dsp-system-using-paddi-2-2q5hkn2ow0.pdf

A multiprocessor DSP system using PADDI-2

Operating systems in embedded wireless communication increasingly must satisfy a tight set of constraints, such as power and real time performance, on heterogeneous software and hardware architectures. In this domain, it is well understood that traditional general-purpose operating systems are not efficient or in many cases not sufficient. More efficient solutions are obtained with OS's that are developed to exploit the reactive event-driven nature of the domain and have built-in aggressive power management. As proof, we present a comparison between two OS's that target this embedded domain: one that is general-purpose multi-tasking and another that is event-driven. Preliminary results indicate that the event-driven OS achieves an 8x improvement in performance, 2x and 30x improvement in instruction and data memory requirement, and a 12x reduction in power over its general-purpose counterpart. To achieve further efficiency, we propose extensions to the event-driven OS paradigm to support power management at the system behavior, system architecture, and architecture module level. The proposed novel hybrid approach to system power management combines distributed power control with global monitoring.

Low power operating system for heterogeneous wireless communication system

In recent years, significant attention has been given to emerging reconfigurable digital signal processing (DSP) systems. They can undergo in-system hardware changes in coder to adapt to post-design external variations in system constraints, stimulus, algorithms, and optimization objectives. This adds degrees of freedom and levels of complexity to the design process that are not well considered by contemporary computer aided design (CAD) methods. This research presents a methodology and CAD design environment, based in a quantitative approach, that support the implementation of domain-specific DSP systems which cope with post-design changes by leveraging reconfigurable hardware architectures. 
Run-time methods and dynamic reconfiguration comes at the costs of overheads. The proposed methodology limits these overheads by imposing a framework that creates multiple pre-characterized templated-mapping design implementations that are organized as candidates under the discrimination of one or more system schedulers. At run-time, the managing scheduler selects implementations according to its assigned optimization objective given the resource availability. To deal with the tight constraints on cost-performance inherent within DSP systems, the framework introduces mapping modes that further guide and/or limit runtime scheduler choice in template selection (dynamic resource "type" allocation), resource binding, and configuration. These modes allow for design-time trade-offs between predictability and flexibility. A formal model that defines the components and their interactions is presented to provide some rigor in the methodology application. 
A design environment and tools development framework is presented that adheres to the methodology and formal model. It includes a simulator for use in quantitative design exploration. The framework accounts for use-costs in computation, communication, and reconfiguration in terms of area, energy, as well as time. Others metrics of interest (such as position, etc.) can be easily incorporated. Detailed quantitative statistics for system behavior are accounted for and visually presented. This aids the designer during iterative design refinement. Moreover, performance metrics can be analyzed at run-time by system schedulers as a guide for statistical-based adaptation. 
The effectiveness of the proposed methodology is demonstrated across a database of generated designs and for an actual multi-user DSP system design. The results for each are presented in separate chapters. The appendix includes a tutorial that discusses the environment, framework, and existing CAD tools.

Design methodology for run-time management of reconfigurable digital signal processor systems

We have constructed a prototype image processing board containing 384 processors in 8 VLSI chips. The goal of the prototype is to show how fine grain parallelism present in image processing applications can be exploited by using lots of simple processors interconnected in clever ways. Each processor has a 16-bit data path, a simple instruction set containing 12 instructions, a simple control unit, and a scan chain for loading data and program. Each VLSI chip, called PADDI-2, contains 48 processors. The programing model used for the processors in MIMD. Each processor has 8 words in the instruction memory. There are internal registers and queues in a processor for storing data and partial results. Data is assumed to be entering the system as a stream and processed by the processors. Each VLSI chip is connected to an external memory (64 K by 16). A hardware synchronization mechanism is used for communication between processors, memory, and the external environment. If a sender and receiver is within the same chip, communication can be done in one cycle by the hierarchical interconnect bus structure. Programming the processors and the interconnections are done at compile time. The board is interfaced to a Sun SPARCstation using the SBus. Video input and output is supported by the board and field buffers are used for buffering. Software tools for checking the board, running test programs at the assembly language level, and libraries for application development have been produced. Image processing applications are currently under development. The board is available for experimentation over the Internet. Further details are available from the project web page (http://infopad.eecs.berkeley.edu/spartan).© (1997) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

MultiPADDI-2 board for image processing

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A multiprocessor DSP system using PADDI-2

Low power operating system for heterogeneous wireless communication system

Design methodology for run-time management of reconfigurable digital signal processor systems

MultiPADDI-2 board for image processing