This article presents PSPHV, a surface-potential-based compact model for laterally diffused MOS (LDMOS) transistors. PSPHV includes a new drain voltage scaling technique that enables accurate modeling of saturation in transistors with nonuniform lateral doping; gate bias-dependent interface charge, which models the gradual channel turn- ON seen in devices with halo doping; internal drain bias clamping, which eliminates the capacitance spikes seen in most existing LDMOS models; and a new avalanche current model for the drift region that accounts for the Kirk effect. PSPHV models the drain expansion effect and diode reverse recovery and is verified against experimental data.

PSPHV: A Surface-Potential-Based Model for LDMOS Transistors

In this work, a scalable robust substrate current model for laterally diffused MOS (LDMOS) transistors is presented. The model is created in two stages. First, a model for intrinsic drain voltage, which accurately captures the modulation of intrinsic drain voltage with applied gate and drain voltages, is developed. This model is then used to derive an expression for the substrate current. The accuracy of the substrate current model is verified by comparing it with the data measured from LDMOS transistors with different device dimensions. The model accurately captures the modulation of substrate current with bias voltages and shows excellent scalability. Different LDMOS designs are also suggested to reduce the substrate current at the same OFF-state breakdown voltage.

Scalable Substrate Current Model for LDMOS Transistors Based on Internal Drain Voltage

This article presents a simple method to create corner models to capture process variations for the lookup table-based MOSFET models through inputs and outputs mapping. The electrical specifications, including the threshold voltage, peak transconductance, ON-state resistance, saturation current, and gate oxide thickness, can be fitted through five model parameters. The effectiveness of the method is demonstrated by both the FinFET model BSIM-CMG and the planar MOSFET measurement data.

A Simple Method to Create Corners for the Lookup Table-Based MOSFET Models Through Inputs and Outputs Mapping

In this work, a detailed characterization of lateral DMOS transistors in the cryogenic regime is carried out. It is shown that carrier freeze-out in the drift region is responsible for increased ON-resistance for temperatures lower than a transition temperature, which is independent of device dimensions. The carrier freeze-out affects the operation of laterally diffused MOS (LDMOS) transistors in the linear region but not in the saturation region due to field-assisted ionization. A peak behavior in output conductance is also observed at cryogenic temperatures. The physics behind these observed anomalous behaviors is studied in detail and modeled. The industry-standard HiSIM_HV2 model is augmented with new equations to extend the model accuracy to 77 K. The accuracy of the model is verified with the data measured from LDMOS transistors with different dimensions. The model accurately captures the device behavior in the 77–300 K temperature range and demonstrates excellent scalability. 

A Physics-Based Compact Model to Capture Cryogenic Behavior of LDMOS Transistors

This paper details a robust parameter extraction flow for the PSPHV LDMOS transistor model. The procedure uses a global scaling parameter set and accounts for self-heating. We describe how to determine parameters associated with important physical effects specific to PSPHV: non-uniform lateral channel doping; the Kirk effect; internal drain voltage clamping; and the drain expansion effect. The method is verified on devices from different technologies. Verilog-A code for PSPHV is publicly available.

/pdf/parameter-extraction-for-the-psphv-ldmos-transistor-model-br85j1y480.pdf

Parameter Extraction for the PSPHV LDMOS Transistor Model

This paper presents an improved modeling method for LDMOS with non-uniform lateral channel doping in three aspects: more accurate DC modeling from a new Vds scaling technique that accounts for the difference in threshold voltage between the source and the drain from non-uniform lateral doping; elimination of spikes in capacitances by clamping the internal drain voltage when the drift region is depleted; and a new avalanche current model for the drift region that accounts for the Kirk effect.

Improved Modeling of LDMOS with Non-Uniform Lateral Channel Doping

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PSPHV: A Surface-Potential-Based Model for LDMOS Transistors

Parameter Extraction for the PSPHV LDMOS Transistor Model

Improved Modeling of LDMOS with Non-Uniform Lateral Channel Doping