An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.

Semiconductor devices and methods of manufacturing the same

The invention provides a process for adjusting the friction coefficient and adhesion between a surface of a first solid object and a surface of a second solid object, which surfaces are movable with respect to each other when the solid objects are in contact with each other, wherein the surface roughness of at least one of the surfaces is adjusted by subjecting one or more selected parts of said first and/or second solidobjects to an electric fieldand/or a magnetic field, wherein at least said one or more selected partsof said first and/or second solid objectscomprise a piezo-electric material, and wherein other parts of said first and/or second solid object do not comprise a piezo-electric material. The invention further provides an object having a surface of which the roughness can be adjusted by subjecting one or more selected parts of the object to an electric fieldand/or a magnetic field, which selected parts comprise a piezo-electric material. In addition, the invention provides a system comprising said object.

Process for adjusting the coefficient of friction and/or adhesion between surfaces of two solid objects

A semiconductor device includes a via structure and a conductive structure. The via structure has a surface with a planar portion and a protrusion portion. The conductive structure is formed over at least part of the planar portion and not over at least part of the protrusion portion of the via structure. For example, the conductive structure is formed only onto the planar portion and not onto any of the protrusion portion for forming high quality connection between the conductive structure and the via structure.

Semiconductor Device and Method of Fabricating the Same

A CMOS image sensor and a method for fabricating the same prevent a lifting effect of microlenses. Also, a diffused reflection of microlenses is prevented. The CMOS image sensor includes photodiodes, an interlayer insulating layer, metal lines formed in the interlayer insulating layer to electrically connect the respective photodiodes with each other, an oxide layer, a passivation layer to protect the CMOS image sensor from external sources, and microlenses formed to pass through the passivation layer at portions corresponding to the photodiodes.

CMOS image sensor and method for fabricating the same

A method for forming shallow trench isolation (STI) for semiconductor devices. A first hard mask is deposited over a semiconductor wafer, and a second hard mask is deposited over the first hard mask. The semiconductor wafer includes a first etching zone and at least a second etching zone disposed beneath the first etching zone. The etch process for the first etching zone and the etch process for the at least one second etching zone are selected such that smooth sidewall surface structures are formed within the semiconductor device. The etch processes for each subsequent etching zone may alternate between non-selective and selective etch processes to preserve at least the first hard mask material.

STI formation for vertical and planar transistors

The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capacitor conductor, and a conductive buried strap in the substrate adjacent the trench top oxide. The trench top oxide includes a doped trench top oxide layer above the conductive strap, and an undoped trench top oxide layer above the doped trench top oxide layer.

Self-aligned buried strap process using doped HDP oxide

A memory cell is formed for a memory cell array that is comprised of a plurality of the memory cells arranged in rows and columns. Deep trenches having sidewalls is formed within a semiconductor substrate. A buried plate region adjoining a deep trench is formed within the semiconductor substrate, and a dielectric film is formed along the sidewalls of the deep trench. A masking layer is patterned such that a portion of the dielectric film is covered by the masking layer and a remaining portion of the dielectric film is exposed. An upper region of the exposed portion of the dielectric film is removed such that a trench collar is formed along a middle portion of a side of the deep trench. The deep trench is partly filled with doped polysilicon. The dopants in the polysilicon diffuse through the side of the deep trench into adjoining regions of the semiconductor substrate during subsequent thermal processing steps to form a buried strap region along a side of the deep trench. The semiconductor substrate is patterned and etched to form at least one isolation trench that adjoins the isolation trench and two of the deep trenches and includes a buried strap region. The patterning uses a mask comprised of a lines and spaces pattern such that at least one active area is defined by the isolation trench and by the deep trench. Each of the lines and the spaces extends across the memory cell array.

Line mask defined active areas for 8F2 dram cells with folded bit lines and deep trench patterns

A method is disclosed for improving etch uniformity in deep silicon etching of a monocrystalline silicon wafer. Such method includes forming a pad dielectric layer on a wafer including monocrystalline silicon, forming a silicon layer over the pad dielectric layer, and then applying a clamp to an edge of the wafer. The silicon layer is then removed except in areas protected by the clamp. Thereafter, a hardmask layer is applied and patterned on the wafer; and the wafer is then directionally etched with the patterned hardmask to etch trenches in the monocrystalline silicon. In such manner, a source of silicon (in the silicon layer) is provided at the wafer edge, such that the silicon loading is improved. In addition, the silicon layer at the wafer edge forms a blocking layer which prevents formation of black silicon.

Method of improving etch uniformity in deep silicon etching

In vertical transistor trench DRAM arrays, the problem of pinching off the transistor bodies in the P-well is addressed by etching a set of trenches between the DRAM cell trenches down to a level below the buried straps, thus blocking the depletion regions from the buried straps from meeting. The trench structure contains conductive material that forms a conductive path from the bodies of the vertical transistors to the lower portion of the P-well.

Bulk contact mask process

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