Several recent works have demonstrated the benefits of through-silicon-via (TSV) based 3D integration [1–4], but none of them involves a fully functioning multicore processor and memory stacking. 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM (see Fig. 10.6.1). Fabrication is done using 130nm GlobalFoundries device technology and Tezzaron TSV and bonding technology. Packaging is done by Amkor. This processor contains 33M transistors, 50K TSVs, and 50K face-to-face connections in 5×5mm2 footprint. The chip runs at 1.5V and consumes up to 4W, resulting in 16W/cm2 power density. The core architecture is developed from scratch to benefit from single-cycle access to SRAM.

3D-MAPS: 3D Massively parallel processor with stacked memory

As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and silicon have different coefficients of thermal expansion (CTE), TSV causes silicon deformation due to different temperatures at chip manufacturing and operating. The widely used TSV fill material is copper which causes tensile stress on silicon near TSV. In this paper, we propose systematic TSV stress aware timing analysis and show how to optimize layout for better performance. First, we generate a stress contour map with an analytical radial stress model. Then, the tensile stress is converted to hole and electron mobility variations depending on geometric relation between TSVs and transistors. Mobility variation aware cell library and netlist are generated and incorporated in an industrial timing engine for 3D-IC timing analysis. It is interesting to observe that rise and fall time react differently to stress and relative locations with respect to TSVs. Overall, TSV stress induced timing variations can be as much as ± 10% for an individual cell. Thus as an application for layout optimization, we can exploit the stress-induced mobility enhancement to improve timing on critical cells. We show that stress-aware perturbation could reduce cell delay by up to 14.0% and critical path delay by 6.5% in our test case.

/pdf/tsv-stress-aware-timing-analysis-with-applications-to-3d-ic-k95ddrv62x.pdf

TSV stress aware timing analysis with applications to 3D-IC layout optimization

Technology scaling will continue, doubling transistor integration capacity every two years, providing billions of transistors to enable novel systems. 3D integration technology will open the doors even further, changing the landscape, allowing heterogeneous integration of diverse technologies, with abundance of energy efficient interconnects to realize affordable complex systems that will continue to deliver higher performance. This paper presents how to exploit this new technology for energy efficient system designs.

3D integration for energy efficient system design

This paper studies various design tradeoffs existing in the monolithic 3D integration technology. Different design styles in monolithic 3D ICs are studied, including transistor-level monolithic integration (MI-TR) and gate-level integration (MI-G). GDSII-level layout of monolithic 3D designs are constructed and analyzed. Compared with its 2D counterparts, MI-TR designs have advantages in footprint area, wire-length, timing, and power, because of the smaller footprint. MI-G design style also demonstrate advantages in area, timing and power over TSV-based designs, because of the smaller size and parasitics of inter-tier vias compared with TSVs. To further take the advantage of monolithic 3D technology, several technology improvement options are also explored. Besides, some possible design challenges with monolithic 3D are also studied, including global variation and signal integrity issues.

http://www.gtcad.gatech.edu/www/papers/06187545.pdf

A design tradeoff study with monolithic 3D integration

Three-dimensional network-on-chips are suitable communication fabrics for high-density 3D many-core ICs. Such networks have shorter communication hop count, compared to 2D NoCs, and enjoy fast and power efficient TSV wires in vertical links. Unfortunately, the fabrication process of TSV connections has not matured yet, which results in poor vertical links yield. In this work, we address this challenge and introduce AFRA, a deadlock-free routing algorithm for 3D mesh-based NoCs that tolerates faults on vertical links. AFRA is designed to be simple, high performance, and robust. The simplicity is achieved by applying ZXY and XZXY routings in the absence and presence of fault, respectively. Furthermore, AFRA, as will be proved, is deadlock-free when all vertical faulty links have the same direction. This enables the routing to save virtual channels for performance rather than scarifying them for deadlock avoidance. Finally, AFRA provides robustness, which means supporting connection for all possible pairs of communicating nodes in high fault rates. AFRA is evaluated, though cycle accurate network simulation, and is compared with planar adaptive routing. Results reveal that AFRA significantly outperforms planar adaptive routing in both synthetic and real traffic patterns. In addition, the robustness of AFRA is calculated analytically.

AFRA: A low cost high performance reliable routing for 3D mesh NoCs

Heat removal and power delivery have become two major reliability concerns in 3D stacked IC technology. For thermal problem, two possible solutions exist: thermal-through-silicon-vias (T-TSVs) and micro-fluidic channel (MFC) based liquid cooling. In case of power delivery, a highly complex power distribution network is required to deliver currents reliably to all parts of the 3D stacked IC while suppressing the power supply noise to an acceptable level. However, these thermal and power networks pose major challenges in signal routability and congestion. This is because the signal, power, and thermal interconnects are all competing for routing space. In this paper, we present a co-optimization methodology for the signal, power, and thermal interconnects for 3D stacked ICs based on design of experiments (DOE) and response surface method (RSM). The goal is to improve performance, thermal, noise, and congestion metrics with our holistic approach. We also provide in-depth comparison between T-TSV and MFC based cooling method and discuss how to employ DOE and RSM to best co-optimize the multi-functional interconnects simultaneously. Categories and Subject Descriptors B.7.2 [Hardware]: Integrated Circuits-Design Aids General Terms Design, Reliability

http://www.gtcad.gatech.edu/www/papers/iccad09-1.pdf

Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs

Missions envisioned for Micro Air Vehicles (MAVs) such as Intelligence, Surveillance and Reconnaissance (ISR) in urban environments require exceptional agility. These missions typically involve ight through or in close proximity to buildings, tunnels and trees, and require the MAVs to maneuver using sharp dives and climbs along with small-radius turns. The small size of MAVs allows such ight operations within con ned space but the control e ectors must provide su cient maneuverability, while maintaining stability, with only limited sensing capability onboard the platform. To meet these challenges, researchers have long been attracted by the amazing attributes of biological systems, such as those exhibited by birds and insects. Birds can y in dense ocks, executing rapid maneuvers with g-loads far in excess of modern ghter aircrafts, and yet never collide with each other, despite the absence of air tra c controllers. This paper introduces a novel framework for the design and control of a Micro Air Vehicle. The vehicle's conceptual design is based on biologically-inspired principles and emulates a dragon y (Odonata-Anisoptera). The author is borrowing ight mechanism features from the dragon y and merging them with indigenous designs in creating a novel version of a Flapping Wing MAV, called the QV. The QV design incorporates the simplicity of mechanical construction and the complexity of a sophisticated multi-layered Hybrid & Linear / Non-Linear controller to achieve extended ight times and improved agility compared to other Rotary and Flapping Wing MAV designs. The paper talks about the design and control features of the proposed QV design and gives an overview on the developmental e orts been made towards the prototyping of the QV yer. The potential applications for such a high endurance vehicle are numerous, including air-deployable mass surveillance in cluster and swarm formations. The disposability of the vehicle would help in battleeld deployment as well, where such a MAV would be made available to soldiers for proximity sensing and threat level assessment. Other applications would include search and rescue operations and civilian law-enforcement.

http://enu.kz/repository/2010/AIAA-2010-3448.pdf

Bio-Inspired Micro Air Vehicle: Design and Control Issues

We describe the design and analysis of 3D-MAPS, a 64-core 3D-stacked memory-on-processor running at 277 MHz with 63 GB/s memory bandwidth, sent for fabrication using Tezzaron's 3D stacking technology. We also describe the design flow used to implement it using industrial 2D tools and custom add-ons to handle 3D specifics.

/pdf/design-and-analysis-of-3d-maps-a-many-core-3d-processor-with-vroq2ab3iw.pdf

Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory

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Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs

Bio-Inspired Micro Air Vehicle: Design and Control Issues

Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory