An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

The present invention is directed to secreted and transmembrane polypeptides and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention and to methods for producing the polypeptides of the present invention.

Secreted and Transmembrane Polypeptides and Nucleic Acids Encoding the Same

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication

An electrically erasable programmable read only memory (EEPROM) having a non conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the EEPROM device. The non conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. The memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and the drain while the source is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and the source while the drain is grounded. Application of relatively low gate voltages combined with reading in the reverse direction greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region. In addition, the memory cell can be erased by applying suitable erase voltages to the gate and the drain so as to cause electrons to be removed from the charge trapping region of the nitride layer. Similar to programming, a narrower charge trapping region enables much faster erase cycles.

Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping

A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally separated by an insulating layer used to form antifuses. In one embodiment, one-half the diode is located in one rail-stack and the other half in the other rail-stack.

Three-dimensional memory array and method of fabrication

Disclosed is fabricating a semiconductor wafer to form a memory array and peripheral area, the array comprising nonvolatile memory devices employing floating gate transistors and the peripheral area comprising CMOS transistors A first layer of conductive material is applied atop insulating layers A dielectric layer is applied atop the first conductive layer for use in floating gate transistors within the array The dielectric layer and first conductive material are etched from the peripheral area, leaving patterned dielectric material and first conductive material in the array A second layer of conductive material is applied atop the wafer to cover the peripheral area and dielectric layer of the array The conductive and dielectric materials of the array are patterned and etched separately from the patterning and etching of conductive material of each of the first and second conductivity type CMOS transistors of the peripheral area As well, the conductive material of the first conductivity type CMOS transistors of the peripheral area are patterned and etched separately from the patterning and etching of each of, a) conductive and dielectric materials of the array, and b) conductive material of the second conductivity type CMOS transistors of the peripheral area Further, the conductive material of the second conductivity type CMOS transistors of the peripheral area are patterned and etched separately from patterning and etching of each of, a) conductive and dielectric materials of the array, and b) conductive material of the first conductivity type CMOS transistors of the peripheral area

Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors

This invention pertains to a method of fabricating a MRAM structure and the resulting structure. The MRAM structure of the invention has the pinned layer recessed within a trench with the upper magnetic layer positioned over it. The method of MRAM fabrication utilizes a spacer processing technique, whereby the upper magnetic layer of the MRAM stack structure is formed between the region defined by the spacers, thereby allowing for self-alignment of the upper magnetic layer over the underlying pinned magnetic layer.

Self-aligned, magnetoresitive random-access memory (MRAM) structure utilizing a spacer containment scheme

Described is an E2 PROM design comprising a channel region and a floating gate comprising P-type polycrystalline silicon. The work function difference between P-type material effectively increases the threshold voltage of the transistor. This alleviates the need for a boron VT adjust implant. Implants of material such as boron to set the threshold voltage are known to correlate with problems such as implant ionization and junction (avalanche) breakdown. These two undesired effects can be decreased or eliminated in devices comprising the invention. An optional phosphorous implant into the substrate would allow the lowering of VT to a desired level.

Semiconductor floating gate device having improved channel-floating gate interaction

A programming method for flash erasable programmable memory devices (flash EPROMs) comprises a first step of erasing the array of cells, then applying a control gate voltage to access a number of control gates. Any number of control gates can be accessed, but accessing four or eight control gates may have advantages. Regardless of the number of control gates accessed, a digit line voltage is applied to access one of the digit lines, which activates a number of cells. The digit line voltage is sensed for a voltage drop, which indicates the presence of at least one over-erased activated cell. If a digit line voltage drop is detected, a sense voltage is applied to each of the activated cells to determine which is over-erased. A heal voltage is applied to the over-erased cell for an interval of time to store electrons on the floating gate of the over-erased cell. The sense voltage is applied to the over-erased cell to determine if the cell remains over-erased, and if the cell remains over-erased the heal voltage is again applied to the over-erased cell. The sense voltage is then applied to the over-erased cell to determine if it remains over-erased.

Programming method for the selective healing of over-erased cells on a flash erasable programmable read-only memory device

A method of forming a non-volatile memory array includes, a) providing first and second floating gate word lines atop a semiconductor substrate, the first and second word lines being adjacent one another and defining transistor active area therebetween, the first and second word lines having inwardly opposing and facing active area sidewall edges, the first and second word lines each comprising respective nitride capping layers having a thickness of at least about 1000 Angstroms; b) providing a nitride spacer layer over the nitride capping layer; c) anisotropically etching the nitride spacer layer to produce insulating sidewall spacers over the first and second word line active area sidewall edges, the anisotropic etching leaving at least a portion of the nitride capping layer covering each of the first and second word lines, the portion of each nitride capping layer joining with one of the sidewall spacers to cover the first and second word line active area sidewall edges and thereby defining a widened mask misalignment area than were such capping layer portions not present; d) providing an oxide layer over the sidewall spacers and capping layer; e) patterning and etching the oxide layer selectively relative to the nitride capping layer and sidewall spacers to define a contact opening to the active area, the contact opening overlapping with at least one nitride capping layer portion on one of the word lines; and f) providing an electrically conductive plug within the contact opening. A non-volatile memory array is disclosed.

Programmable non-volatile memory cell and method of forming a non-volatile memory cell

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