This paper presents a novel design of a coprocessor that performs hardware-accelerated task scheduling for embedded real-time systems consisting of mixed-criticality real-time tasks. The proposed s...

A Novel On-Chip Task Scheduler for Mixed-Criticality Real-Time Systems

Real-time embedded systems that combine processes of various criticalities (i.e. mixed-criticality real-time systems) represent an emerging research that faces many issues. This paper describes a new ASIC design of a coprocessor that realizes process scheduling for mixed-criticality real-time systems. The solution proposed in this paper uses Robust Earliest Deadline (RED) algorithm. Due to the on-chip implementation of the scheduler, all scheduler operations always take two clock cycles to execute. The proposed solution was verified by simulations that applied millions of random inputs. Chip area costs are evaluated by synthesis into ASIC using 28 nm TSMC technology. The proposed RED-based scheduler is compared with an existing EDF-based scheduler that supports hard realtime processes only. Even though the RED-based scheduler costs more chip area, it can handle any combinations of process criticalities, variations of process execution times and deadlines, achieves higher CPU utilization and can be used for scheduling of non-real-time, soft real-time and hard real-time processes combined within one system.

/pdf/red-based-scheduler-on-chip-for-mixed-criticality-real-time-3whj0u8sbf.pdf

RED-based Scheduler on Chip for Mixed-Criticality Real-Time Systems

With the development of 5G communication technology, more and more applications could be integrated into one system. Edge computing system and mixed-criticality system may integrate tasks of different criticality levels, which brings better balance in isolation and performance. Such advantages make it gradually become a research hotspot in edge computing and real-time systems with 5G. The important content of designing a mixed-criticality system is how to reduce interference between tasks and how to schedule tasks efficiently to ensure that tasks of different criticality levels can meet time constraints. Instruction extension and hardware software cooperative support may be an effective solution. Based on a fine-grained multithreaded RISC-V processor, this article gives some extensions for real-time operations and proposes a hardware software cooperative real-time scheduling mechanism. Experimental results show that, compared with FlexPRET hardware, the performance of thread scheduling is improved by 22.94% on average. Compared with software scheduling, the performance of scheduling same programs and multiple programs are improved by 15.46% and 26.00%, respectively.

/pdf/embedded-microprocessor-extension-design-and-optimization-2odzj3jw.pdf

Embedded Microprocessor Extension Design and Optimization for Real-Time Edge Computing

Abstract To address the question of how to deliver time-sensitive software for Cyber-Physical Systems (CPS) requires a range of modelling and analysis techniques to be developed and integrated. A number of these required techniques are unique to time-sensitive software where timeliness is a correctness property rather than a performance attribute. This paper focuses on how to obtain worst-case estimates of the software’s execution time; in particular, it considers how workload models are derived from assumptions about the system’s run-time behaviour. The specific contribution of this paper is the exploration of the notion that a system can be subject to more than one workload model. Examples illustrate how such multi-models can lead to improved schedulability, and hence more efficient CPS. An important property of the approach is that the derived analysis exhibits model-bounded behaviour. This ensures that the maximum load on the system is never higher than that implied by the individual models. 

pdf/multi-model-workload-specifications-and-their-application-to-vcrjtksucb.pdf

Multi-Model Workload Specifications and their application to Cyber-Physical Systems

Mixed-criticality real-time systems represent an emerging technology that faces many research issues. In this paper, a new coprocessor unit that realizes FPGA-accelerated task scheduling for mixed-criticality real-time embedded systems consisting of tasks of various deadlines, priorities and criticalities is presented. We propose an FPGA-based task scheduler that implements an existing algorithm called Robust Earliest Deadline and previously developed hardware architectures used for scheduling of real-time tasks that implement other algorithms. Due to the hardware implementation of the scheduler, the duration of scheduler operations is always constant (2 clock cycles) regardless of the task amount within the system. The proposed scheduler was verified by simulations that applied millions of random inputs. Resource costs of the proposed solution are evaluated within an Intel Cyclone V FPGA synthesis. Two versions of task schedulers were compared and analyzed: existing EDF scheduler applicable for hard RT tasks only and the proposed RED scheduler. According to synthesis results, the proposed solution consumes 235% to 397% more look-up tables and 44 % to 171 % more registers than the EDF scheduler with equivalent parameters used. However, the proposed scheduler provides performance and can handle any combination of non-RT, soft RT and hard RT tasks together in the same system, which is achievable by state of the art.

FPGA-based Task Scheduler for Mixed-Criticality Real-Time Systems

The System-on-Chip revolution has not impacted the field of safety-critical systems as widely as the rest of the electronics market. However, it is nowadays acknowledged that sharing resources between applications of different criticality is a key leverage to reduce costs and improve performance. Certification of systems hosting such mixed-criticality application sets requires sufficient isolation between criticality levels, i.e. a low-critical task must not cause a fault in a high-critical task, especially a temporal fault, which is likely when several co-running tasks compete for a shared resource. This digest describes implementation schemes which can be included, at both hardware and software levels, in mixed-critical systems to enforce such isolation.

Resource Management for Mixed-Criticality Systems on Multi-core Platforms with Focus on Communication

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Resource Management for Mixed-Criticality Systems on Multi-core Platforms with Focus on Communication