Robert Wieland

TL;DR: The I_nterC_hip V_ia (ICV) as mentioned in this paper is a fully CMOS compatible wafer-scale process which provides vertical electrical interchip interconnects placed at arbitrary locations, without intervention to the IC's fabrication technologies.

TL;DR: In this article, the fabrication steps for wafer level processing of silicon interposers with copper filled TSVs as well as their wafer-level assembly with IC components are presented, and special focus is drawn on the TSV formation process including via etching, isolation and filling, front side high density wiring and subsequent backside processing of the thin TSV wafers.

TL;DR: In this paper, a low-cost fabrication approach for vertical system integration is introduced, which takes advantage of wafer level processing to avoid increasing package sizes and expensive single component assembling processes.

TL;DR: 3D integrated systems show reduced chip areas and enable optimized partitioning, both which decrease the fabrication cost of the system and an additional benefit is the enabling of minimal interconnection lengths and the elimination of speedlimiting inter-chip interconnects.