While hardware caches are generally effective at improving application performance, they greatly complicate performance prediction. Slight changes in memory layout or data access patterns can lead to large and systematic increases in cache misses, degrading performance. In the worst case, these misses can effectively render the cache useless. These pathological cases, or ``cache risk patterns'', are difficult to predict, test or debug, and their presence  limits the usefulness of caches in safety critical real-time systems, especially in hard real-time environments.In this paper, we explore the effect of randomized cache replacement policies in real-time systems with stringent timing constrains. We present simulation-based results on representative examples that illustrate the problem of performance anomalies with standard cache replacement policies. We show that, by eliminating dependencies on access history, randomized replacement greatly reduces the risk of these cache-based performance anomalies, enabling probabilistic worst-case execution time analysis.

/pdf/using-randomized-caches-in-probabilistic-real-time-systems-4h8734z65n.pdf

Using Randomized Caches in Probabilistic Real-Time Systems

Performance tuning becomes harder as computer technology advances. One of the factors is the increasing complexity of memory hierarchies. Most modern machines now use at least one level of cache memory. To reduce execution stalls, cache misses must be very low. Software techniques used to improve locality have been developed for numerical codes, such as loop blocking and copying. Unfortunately, the behavior of direct mapped and set associative caches is still erratic when large data arrays are accessed. Execution time can vary drastically for the same loop kernel depending on uncontrolled factors such as array leading size. The only software method available to improve execution time stability is the copying of frequently used data, which is costly in execution time. Users are not usually cache organization experts. They are not aware of such phenomena and have no control over it. In this paper, we show that the recently proposed four-way skewed associative cache yields very stable execution times and good average miss ratios on blocked algorithms. As a result, execution time is faster and much more predictable than with conventional caches. It is therefore possible to use larger block sizes in blocked algorithms, which will further reduce blocking overhead costs.

Skewed associativity improves program performance and enhances predictability

Existing timing analysis techniques to derive Worst-Case Execution Time (WCET) estimates assume that hardware in the target platform (e.g., the CPU) is fault-free. Given the performance requirements increase in current Critical Real-Time Embedded Systems (CRTES), the use of high-performance features and smaller transistors in current and future hardware becomes a must. The use of smaller transistors helps providing more performance while maintaining low energy budgets, however, hardware fault rates increase noticeably, affecting the temporal behaviour of the system in general, and WCET in particular. In this paper, we reconcile these two emergent needs of CRTES, namely, tight (and trustworthy) WCET estimates and the use of hardware implemented with smaller transistors. To that end we propose the Degraded Test Mode (DTM) that, in combination with fault-tolerant hardware designs and probabilistic timing analysis techniques, (i) enables the computation of tight and trustworthy WCET estimates in the presence of faults, (ii) provides graceful average and worst-case performance degradation due to faults, and (iii) requires modifications neither in WCET analysis tools nor in applications. Our results show that DTM allows accounting for the effect of faults at analysis time with low impact in WCET estimates and negligible hardware modifications.

/pdf/dtm-degraded-test-mode-for-fault-aware-probabilistic-timing-1a5pcopq7t.pdf

DTM: Degraded Test Mode for Fault-Aware Probabilistic Timing Analysis

Skewed-associative caches have been shown to statisticaly exhibit lower miss ratios than set-associative caches at equal associativity degrees. But for L1 caches, the performance of a four-way set-associative cache is known to be quite close to that of a 16-way set-associative cache. In this paper, we first show that BTBs and L2 caches featuring long line size may benefit a lot from a high associativity degree on set-associative caches and a LRU replacement policy. Skewed-associative caches with an hypothetic LRU replacement policy «provide» this high associativity but with a low number of cache banks. Unfortunately, LRU replacement policies can not be easily implemented in hardware on skewed-associative caches. We propose some new replacement heuristics for skewed-associative caches. Those heuristics exhibit slightly worse behavior than a full LRU replacement policy, but still allow a 2-way skewed-associative cache to outperform a 4-way LRU set-associative cache and a 4-way skewed-associative cache to outperform a 16-way LRU set-associative cache. Therefore skewed-associativity allows significant miss reduction on BTBs and L2 caches.

https://hal.inria.fr/inria-00073481/document

A New Case for Skewed-Associativity

cache memory, associative, stride, random, hashing, set lookup, data placement This paper presents a design for a randomized, placement-insensitive, data cache and analyzes its performance An address stream is randomized using a hash function which selects a set in an associative cache The manipulation of large data structures is modeled by traversal of a cyclic sweep address sequence and the miss ratio is accurately determined for this sequence A purely analytic approach to determine cache performance is developed Analysis predicts regions in which a placement-insensitive cache operates with very few cache misses A pseudo-random hash function is presented and used to randomize addresses into cache sets and a counting technique is used to determine miss ratios Finally, an actual cache is simulated allowing comparison against theory A matrix multiply program is studied demonstrating a close relationship between analysis and at least one real application

http://www.hpl.hp.com/techreports/93/HPL-93-41.pdf

Randomization and Associativity in the Design of Placement-Insensitive Caches

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Randomization and Associativity in the Design of Placement-Insensitive Caches