Robert Floyd Payne
Texas Instruments
78 Papers
1.1K Citations
Robert Floyd Payne is an academic researcher from Texas Instruments. The author has contributed to research in topics: Dielectric & Signal. The author has an hindex of 17, co-authored 78 publications.
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Papers
Patent
Interchip communication using a dielectric waveguide
Juan Alejandro Herbsommer,Robert Floyd Payne,Marco Corsi,Baher S. Haroun,Hassan H. Ali +4 more
- 04 Apr 2013
TL;DR: In this paper, a circuit assembly with a package substrate (304-A) and an integrated circuit (IC) (302-A), where the IC is secured to the package substrate and is electrically coupled to the microstrip line.
165
Patent
Dielectric waveguide with non-planar interface surface and mating deformable material
Juan Alejandro Herbsommer,Gerd Schuppener,Robert Floyd Payne +2 more
- 01 Apr 2013
TL;DR: In this article, a dielectric wave guide (DWG) is configured in a non-planer shape for mating with a second DWG having a matching nonplanar shaped mating end.
137
A 6.25-Gb/s binary transceiver in 0.13-/spl mu/m CMOS for serial data transmission across high loss legacy backplane channels
Robert Floyd Payne,Paul E. Landman,Bhavesh G. Bhakta,Srinath Ramaswamy,Song Wu,John Powers,Mustafa Ulvi Erdogan,Ah-Lyan Yee,R. Gu,Lin Wu,Yiqun Xie,B. Parthasarathy,Keith Brouse,W. Mohammed,K. Heragu,V. Gupta,L. Dyson,Wai Lee +17 more
TL;DR: In this article, a transceiver capable of 6.25-Gb/s data transmission across legacy communications equipment backplanes is described, which can compensate up to 20 dB of channel loss to remove intersymbol interference.
131
Patent
Interpolator based clock and data recovery (CDR) circuit with digitally programmable BW and tracking capability
Robert Floyd Payne,B. Parthasarathy +1 more
- 17 Feb 2004
TL;DR: In this article, a rate programmable divider circuit (606,656,706 ) that operates over a wide range of clock and data rates (e.g., 800 ) to provide various phase correction step sizes at a fixed VCO clock frequency is presented.
56
A 6.25Gb/s binary adaptive DFE with first post-cursor tap cancellation for serial backplane communications
Robert Floyd Payne,Bhavesh G. Bhakta,Srinath Ramaswamy,Song Wu,John Powers,Paul E. Landman,Ulvi Erdogan,Ah-Lyan Yee,R. Gu,Lin Wu,Yiqun Xie,B. Parthasarathy,Keith Brouse,W. Mohammed,K. Heragu,V. Gupta,L. Dyson,Wai Lee +17 more
- 29 Aug 2005
TL;DR: A 6.25 Gb/s serial receiver with a 4-tap adaptive DFE is implemented in a 0.13 /spl mu/m 7LM CMOS process, enabling recovery of a data eye fully closed from channel losses and crosstalk.
52