A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

Method and apparatus for performing multiply-add operations on packed data

An audio information processing subsystem (200) is disclosed which includes a stream processor (100) for simultaneously processing multiple streams of audio data. Processing subsystem (200) also includes a program memory (202) coupled to stream processor (100) for storing instructions for controlling processing system (200) and a data memory (203/204) also coupled to stream processor (100). Additionally, a direct memory access circuitry (208) is provided for controlling direct memory accesses to a selected one of program memory (202) and data memory (203/204).

Circuits, system, and methods for processing multiple data streams

Programmable processor and method with wide operations

A general purpose processor with four copies of an access unit, with an access instruction fetch queue A-queue (101-104). Each A-queue (101-104) is coupled to an access register file AR (105-108) which is coupled to two access functional units A (109-116). In a typical embodiment, each thread of the processor may have on the order of sixty-four general purpose registers. The access unit functions independently for four simultaneous threads of execution, and each compute control flow by performing arithmetic and branch instructions and access memory by performing load and store instructions. These access units also provide wide specifiers for wide operand instructions. These eight access functional units A (109-116) produce results for access register files (105-108) and memory addresses to a shared memory system (117-120).

System with wide operand architecture, and method

A method and an apparatus for configuring arbitrary sized data paths comprising multiple context processing elements (MCPEs) are provided. Multiple MCPEs may be chained to form wider-word data paths of arbitrary widths, wherein a first ALU serves as the most significant byte (MSB) of the data path while a second ALU serves as the least significant byte (LSB) of the data path. The ALUs of the data path are coupled using a left-going, or forward, carry chain for transmitting at least one carry bit from the LSB ALU to the MSB ALU. The MSB ALU comprises configurable logic for generating at least one signal in response to a carry bit received over the left-going carry chain, the at least one signal comprising a saturation signal and a saturation value. The MCPEs of the data path use configurable logic to manipulate a resident bit sequence in response to the saturation signal transmitted thereby reconfiguring, or changing the operation of, the data path in response to the saturation signal. The carry chains support carry operations for non-local functions comprising minimum and maximum arithmetic functions.

Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements

An integrated circuit multiplier-accumulator architecture includes an M-bit wide register for inputting an X operand and an N-bit wide input register for inputting a Y operand to a multiplier The multiplier can selectably multiply or concatenate the operands to produce a binary product in the form of a first array of M+N parallel bits A binary adder adds the binary product to a second array of M+N+P+1 parallel bits and outputs the sum as a Z result in the form of a third array of M+N+P+1 parallel bits The Z result is stored in a selected one of two accumulators A feedback path is provided to output selected accumulator contents to the adder as the second binary array of M+N+P+1 bits Output ports are provided for outputting a selected portion of the accumulator contents Preferably, the output ports can output the entire M+N+P bits in parallel, as well as any selected portion thereof Overflow logic can be provided which determines from the (M+ n+P+1)th bit whether an overflow has occurred in the M+N+P bit result A format adjust circuit is provided between the accumulators and the output ports for shifting the entire output accumulator contents a predetermined number of bits within a range of zero to at least P bits, and preferably P+1 bits, in the direction of the most significant bit

Fixed-point multiplier-accumulator architecture

A high-speed digital multiplier architecture is implemented in a bipolar very large scale integrated circuit technology. Operand input and product output latches are independently enabled by inverted clock signals. The multiplier can be operated in unclocked, separately clocked and single clock or master-slave modes of operation. The multiplier can be operated to concatenate, rather than multiply, the operands and thereby load the operands directly from the inputs to the output. A selectable format adjust performs a one bit left shift on the product. A low order zero bit is inserted in the shifted product, an overflow flag is set in case the product is -1.0×-1.0=1.0, and rounding is correct for both adjusted and unadjusted products. A zero flag is provided which is correct for both rounded and unrounded output products. A negative flag provides an unambiguous indicator of product sign in signed and mixed mode or format adjusted operation.

High-speed digital multiplier architecture

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Fixed-point multiplier-accumulator architecture

High-speed digital multiplier architecture