Robert E. Murray
IBM
8 Papers
485 Citations
Robert E. Murray is an academic researcher from IBM. The author has contributed to research in topics: Translation lookaside buffer & Pipeline burst cache. The author has an hindex of 7, co-authored 8 publications.
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Papers
Patent
Apparatus and method for TLB purge reduction in a multi-level machine system
Patrick Melvin Gannon,Peter Hermon Gum,Roger Eldred Hough,Robert E. Murray +3 more
- 26 Aug 1993
TL;DR: In this paper, a system for reducing purging of a translation lookaside buffer (TLB) to reduce operating system overhead in a system running multiple levels of virtual machines is presented.
178
Patent
Multiprocessing system including gating of host I/O and external enablement to guest enablement at polling intervals
Roger Eldred Hough,Robert E. Murray +1 more
- 14 Dec 1994
TL;DR: In this article, a data processing system operating under a multiprocessing hypervisor program subject to I/O interrupts during a polling interval of the program includes one or more processors for executing the hypervisor programs and host system and one or multiple guest systems under the hyper-visor program.
119
Patent
Method and apparatus for enabling an interpretive execution subset
Geoffrey Owen Blandy,Lisa C. Heller,Robert E. Murray +2 more
- 23 Oct 1990
TL;DR: In this article, an apparatus and method for recognizing guest virtual machines which require only a subset of interpretive execution facilities is established for short duration jobs and a reduction of initialization and termination overhead creates a substantial performance improvement.
56
Patent
Method for transferring data between processors on a network by establishing an address space for each processor in each other processor's
Thomas A. Gregg,Robert Stanley Capowski,Frank D. Ferraiolo,Marten Jan Halma,Thomas H. Hillock,Robert E. Murray +5 more
- 17 Jun 1994
TL;DR: A multi-system interconnect facility in which each central processor complex in the system has an assigned storage space for each other central processor complexes for use in communicating with each other processor complex is described in this paper.
54
Patent
Transparent processor sparing
Timothy J. Slegel,Robert E. Murray +1 more
- 30 Apr 1998
TL;DR: In this article, the micro-architected state of a processor is extracted and returned to the system where that state can be loaded into a spare processor in the system and processing resumed without interruption.
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