Robert E. Jones
Freescale Semiconductor
40 Papers
720 Citations
Robert E. Jones is an academic researcher from Freescale Semiconductor. The author has contributed to research in topics: Die (integrated circuit) & Layer (electronics). The author has an hindex of 20, co-authored 40 publications.
Chat about Author
Papers
Analytical and Numerical Modeling of the Thermal Performance of Three-Dimensional Integrated Circuits
TL;DR: Analytical and finite-element models of heat transfer in stacked 3D ICs are developed and it is shown that package and heat sink thermal resistances play a more important role in determining temperature rise compared to thermal resistsances intrinsic to the multidie stack.
172
Patent
Self-aligned magnetic clad write line and its method of formation
Robert E. Jones,Carole Barron,E. Luckowski,Bradley M. Melnich +3 more
- 03 Mar 2003
TL;DR: In this paper, a self-aligned magnetic bit line structure for a magnetic memory element and its method of formation are disclosed, wherein the selfaligned magnetic clad bit line structures (274) extends within a trench (258) and includes a conductive material (264), magnetic cladding sidewalls (262) and a magnetic claddings cap (252).
129
Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits
TL;DR: In this article, the authors present a comprehensive analysis of the electrical properties of through silicon vias and microconnects with an emphasis on single via characteristics as well as inter-TSV capacitive and inductive coupling in the presence of either a neighboring ground tap or a grounded substrate back plane.
88
Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits
Ioannis Savidis,Syed M. Alam,Ankur Jain,Scott K. Pozder,Robert E. Jones,Ritwik Chatterjee +5 more
- 01 Dec 2008
TL;DR: A comprehensive analysis of the electrical properties of through silicon vias and microconnects with an emphasis on single via characteristics as well as inter-TSV capacitive and inductive coupling in the presence of either a neighboring ground tap or a grounded substrate back plane is presented.
78
Thermal modeling and design of 3D integrated circuits
Ankur Jain,Robert E. Jones,Ritwik Chatterjee,Scott K. Pozder,Zhihong Huang +4 more
- 28 May 2008
TL;DR: In this paper, an analytical model for temperature distribution in a multi-die stack with multiple heat sources is developed, and the analytical model is used to extend the traditional concept of thermal resistance in an IC to thermal resistance and thermal sensitivity matrices for a 3D IC.
67