An i-GaN layer (electron transit layer), an n-GaN layer (compound semiconductor layer) formed over the i-GaN layer (electron transit layer), and a source electrode, a drain electrode and a gate electrode formed over the n-GaN layer (compound semiconductor layer) are provided. A recess portion is formed inside an area between the source electrode and the drain electrode of the n-GaN layer (compound semiconductor layer) and at a portion separating from the gate electrode.

Compound semiconductor device and manufacturing method of the same

In a high electron mobility transistor, with a normally-off operation maintained, on-resistance can be sufficiently reduced, so that the performance of a semiconductor device including the high electron mobility transistor is improved. Between a channel layer and an electron supply layer, a spacer layer whose band gap is larger than the band gap of the electron supply layer is provided. Thereby, due to the fact that the band gap of the spacer layer is large, a high potential barrier (electron barrier) is formed in the vicinity of an interface between the channel and the electron supply layer.

Semiconductor device and method of manufacturing the same

A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A diffusion barrier layer is disposed on top of the second III-V compound layer. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode.

High electron mobility transistor and method of forming the same

Provided is a nitride semiconductor device including: a nitride semiconductor layer over a substrate wherein the nitride semiconductor has a two-dimensional electron gas (2DEG) channel inside; a drain electrode in ohmic contact with the nitride semiconductor layer; a source electrode in Schottky contact with the nitride semiconductor layer wherein the source electrode is spaced apart from the drain electrode; a floating guard ring in Schottky contact with the nitride semiconductor layer between the drain electrode and the source electrode; a dielectric layer formed on the nitride semiconductor layer between the drain electrode and the source electrode and on at least a portion of the source electrode wherein the dielectric layer is applied to the floating guard ring between the drain electrode and the source electrode; and a gate electrode formed on the dielectric layer to be spaced apart from the drain electrode, wherein a portion of the gate electrode is formed over a drain-side edge portion of the source electrode with the dielectric layer interposed therebetween, and a manufacturing method thereof.

Nitride semiconductor device and manufacturing method thereof

An Enhancement-mode (E-mode) high electron mobility transistor (HEMT) includes a channel layer with a 2-Dimensional Electron Gas (2DEG), a barrier layer inducing the 2DEG in the channel layer, source and drain electrodes on the barrier layer, a depletion layer on the barrier layer between the source and drain electrodes, and a gate electrode on the depletion layer. The barrier layer is recessed below the gate electrode and the depletion layer covers a surface of the recess and extends onto the barrier layer around the recess.

E-Mode High Electron Mobility Transistors And Methods Of Manufacturing The Same

An enhancement-mode GaN transistor, the transistor having a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate containing acceptor type dopant elements, and a diffusion barrier comprised of a III Nitride material between the gate and the buffer layer.

Back diffusion suppression structures

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Back diffusion suppression structures