This paper presents a base for a human rescue system during disasters using multiple machine communication. A method of Long-Range Networking of robots controlled by supervised machines is used. A series of automated robots communicate with each other to detect the human presence and priorities the situation. Using the data acquired from the scene the information is given to the rescue organization for further actions to be taken. I2C protocol is used as the base for communication. Automated communication has been introduced using unidirectional communication. An ultra-long-range communication has been implemented using low power LoRa module.

Unidirectional Communication of Long-Range Network of Robots

The article discusses the design process of the bus bridge between internal APB bus of the central processing unit implemented by means of field-programmable gate array and the external peripherals. On the one hand, the designed bridge offers scalability and can be used anywhere. On the other hand, the authors attempt to reflect on the possible usage of the module in design of IEC 61131-3-based programmable logic controller. The design problems, assumptions and possibilities of the designed IP core are presented.

FPGA-based implementation of APB/SPI bridge

Increasing demand of multimedia functions in mobile influenced systems provides limitations to battery usage in terms of power. To overcome this problem SLIMbus is designed by MIPI alliance which gives higher bus bandwidth by supporting more number of data channels, supports clock gear mechanism that gives less power consumption in hand held devices by changing the clock frequency dynamically. SLIMbus device controller provides the interfacing with external peripheral devices by using any serial interface here I2C interfacing is used. It used TDM frame structure and multidrop topology to connect more components simultaneously.

Design & verification of serial low-power inter-chip media bus (SLIMbus) device controller supporting MIPI standard

In this research the master-slave method implemented on an embedded system using 3 processor applied to the mobile robot, to know the speed of program execution of robot. As a comparison is also used a robot with an embedded system based on single processor. From the experimental results, by applying the slave master method obtained the execution time of 546,5 μs and the number of iteration 1079, while for single processor-based system obtained execution time average 67828 μs and the amount of iteration average 147 times. Where the number of iterations is obtained by running the robot for 10 s. From this experiment, it can be concluded that there is a performance increase of 7.3% when compared to embedded systems based on single processor.

/pdf/implementation-of-master-slave-method-on-multiprocessor-3arn0b3yuw.pdf

Implementation of master-slave method on multiprocessor-based embedded system: case study on mobile robot

For mobile, automotive, and Internet of Things devices, the exponentially growing number of sensors present new design difficulties. Both the overall pin count and the bandwidth needs have greatly grown because of these difficulties. The I3C interface, which uses a single 2-wire high-speed connection to connect all the system’s sensors, was developed by the MIPI Alliance to address these issues. It complies with the MIPI I3C specification and backwards compatible with the I2C standard. The Master Controller is designed to enhance sensor communication capabilities easily and quickly with improved performance and power efficiency in any mobile SoC device. When compared to existing designs, it uses less energy and performs better. The hardware and software components of the Master Controller are separated. Hardware-based packet formation and message handling are handled by the I3C manager. It supports 32-bit APB slave mode to access the registers interface and external DMA and has an interconnect protocol. To lessen the stress on the host handling the I3C interface, a FIFO is optional. With optional secondary master support, it primarily serves as a master controller. Slave bus controller, common command codes controller, and frame generator make up the Slave Controller’s three main modules. The slave device supporting high data rate / dual data rate implements the APB interface and provides a basic payload control mechanism FIFO for the read and write data. This project proposes the design and implementation of MIPI I3C Master Controller using Verilog HDL which will be simulated and implementation using Xilinx Vivado Spartan 7 FPGA. 

Design and Implementation of MIPI I3C master controller SubSystems

All design unit consists of smaller functional blocks called subsystems or module. For effective functioning of the system these modules need to be in sync with each other and share re-sources. Problem starts when one subsystem follows different protocol as others. Each module has its different bit rate or baud rate of data transfer which can be either asynchronous or synchronous. The paper describes an architecture which defines how to transfer the data from one protocol to another protocol. It exploits the flexible protocols of I2C which makes it compatible with APB AMBA protocol. The proposed architecture is a bridge between I2C Master and APB Salve and can transfer data from I2C supported module to APB supported module and vice-versa. The data travels from a serial bus (I2C) to parallel bus (APB) to serial (I2C) in sync with the respective domain clock. This forms a bidirectional interface between I2C supported module and APB supported module.

Implementing Communication Bridge between I2C and APB

Analyzing the Impact of Different Composite Dielectrics on Performance Parameters of a Magnetic Tunnel Junction Memory Device

To catch up pace with development in processors, power consumption of a memory module is often amortized for higher bandwidth and lower latencies. As a result memory module consumes a major fraction of total power consumption in a system. This has led to low power design. This paper will evaluates three new DRAM interface, viz. MemBlaze, MemCorrect and MemDrowsy, developed at Stanford University, USA. Paper intends to extract out know-hows, tradeoffs incurred, and energy saving mode, hardware overheads and application area of the interfaces. All the three architectures work on reducing wakeup latencies of a Power-Up mode in DRAM, thus allowing the DRAM to use their Power-Down modes rigorously. The technique is capable of reducing the background power consumption up to 50%. The interface finds its application in the field which demands heavy memory usage like that of data centric applications, server memories, handling Big Data and Online Transaction Processing (OLTP) and Online Analytical Processing (OLAP).

Power reduction strategies for DRAM used in data centric applications

A promising area for developing devices beyond conventional metal-oxide-semiconductor (CMOS) technology is spintronics, which uses the spin degree of electrons as the information vector. The advent of 2-dimensional materials has given spintronic devices unique platforms, and numerous innovative and novel application concepts have been presented. This article evaluates the effect of adding composite dielectrics (ZrO2 or TiO2 or Ta2O5) to the MgO dielectric layer to create a MgO-ZrO2/TiO2/Ta2Os-MgO composite dielectric layer. Non-equilibrium Green's function (NEGF) driven simulator is used to run the simulations. The important transport properties of the MTJ, such as the anti-parallel and parallel resistances, anti-parallel and parallel differential resistances, TMR, differential TMR, and both the out-of-plane and in-plane spin transfer torques (STT) have been calculated using simulator based on NEGF quantum transport. To examine the reliability and performance of the MTJ model under the temperature variation, the temperature-related analysis of TMR has been analyzed for both the conventional and proposed MTJ models. Interestingly, the maximum TMR at 13 K and at room temperature is obtained for the Tu2O5-based composite dielectric MTJ model, with 549% and 282% respectively. Hence, the design of the MTJ memory with a Taz2O5-based composite dielectric composition is found to be superior.

Enhanced Performance Parameters of Magnetic Tunnel Junction with Composite Dielectric Barrier

Noise processing and diagnostics of a spintronic-based IOT sensor for magnetocardiography application using SpintronCardioNet

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