The B Book

Internet of Things (IoT) devices play a crucial role in the overall development of IoT in providing countless applications in various areas. Due to the increasing interest and rapid technological growth of sensor technology, which have certainly revolutionized the way we live today, a need to provide a detailed analysis of the embedded platforms and boards is consequential. This paper presents a comprehensive survey of the recent and most-widely used commercial and research embedded systems and boards in different classification emphasizing their key attributes including processing and memory capabilities, security features, connectivity and communication interfaces, size, cost and appearance, operating system support, power specifications, and battery life and listing some interesting projects for each device. Through this exploration and discussion, readers can have an overall understanding on this area and foster more subsequent studies.

A Review of Low-End, Middle-End, and High-End Iot Devices

A high performance real-time Interferometry Sensor System Architecture

Continued technology scaling in VLSI has enabled more and more computation cores to be integrated in the same chip. This has facilitated the parallelization of processing and the increase of performance whilst keeping energy consumption at reasonable levels. To study the potential improvement of performance in such many core systems, three existing models have been popular in both the research community and industry. Amdahl's law is the original speedup model that estimates the maximum performance improvement with fixed workloads. Gustafson's law is a popular model that introduces variable workloads and estimates fixed time speedup. Sun and Ni combined the above two models into one considering the memory-bounded situation. These models are further extended via the Hill-Marty model to cover a limited form of heterogeneity. This paper extends these models to cover a more comprehensive assumption of core heterogeneity. We also present power and energy models based on the extended heterogeneous models. Our models cover popular power and performance control methods such as Dynamic Voltage Frequency Scaling (DVFS), power gating, etc. A case study is performed with an ARM big.LITTLE architecture containing Cortex A7 and A15 cores, including a comprehensive analysis with different ratios of parallel and sequential workloads to identify the most energy-efficient system configuration based on these models. Experimental results demonstrated high correlations between practically measured power normalized performance and that of the proposed extended models.

Power and Energy Normalized Speedup Models for Heterogeneous Many Core Computing

Traditional hierarchical modelling methods tend to have layers of abstraction corresponding to naturally existing layers of concern in multi-level systems. Although logically and functionally intuitive, this is not always optimal for analysis and design. For instance, parts of a system in the same logical layer may not contribute to the same degree on some metric, e.g. system power consumption. When focusing on a specific parameter or set of parameters, to moderate the analysis, design and runtime effort, less significant parts of the system should be modelled at higher levels of abstraction and more significant ones with more detail. This parametric significance-driven modelling approach focuses more on optimal parametric fidelity than on logical intuition. Using system power consumption as an example parameter, this paper presents Order Graphs (OGs), which have a clear hierarchical structure, and provide straightforward vertical zooming across multiple layers (orders) of model abstraction, resulting in the discovery of power-proportional cuts that run through different orders to be analysed together in a flat manner. Stochastic Activity Networks (SANs), a good flat modelling method, is suggested as an example of studying techniques for cuts discovered with OGs. A series of experiments on an Odroid development system consisting of an ARM big.LITTLE multi-core structure provides initial validation for the approach.

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Order Graphs and Cross-Layer Parametric Significance-Driven Modelling

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Experiments with Odroid-XU3 board

The efficiency and maintainability of fault tolerance mechanisms in a computer system has typically not been a major topic of concern, mostly because fault tolerance is a non-functional system requirement. This paper proposes a Holistic Fault Tolerance architecture, based on a centralised fault tolerance management, with related functionality distributed across the entire system. The most suitable error detection and error recovery strategies for a given application are chosen by a special crosscutting controller depending on error rates, system performance and resource utilisation requirements. We discuss the motivation for introducing this holistic fault tolerance architecture and reason about its benefits from the point of view of optimal system operation and improved maintainability. The advantages and possible implementation challenges of the proposed approach are demonstrated by a real-world application.

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Architecting Holistic Fault Tolerance

Computer systems are developed taking into account that they should be easily maintained in the future. It is one of the main requirements for the sound architectural design. The existing approaches to introducing fault tolerance rely on recursive system structuring out of functional components – this typically results in non-optimal fault tolerance. The paper proposes a vision of structuring complex many-core systems by introducing a special component supporting system-wide fault tolerance coordination. The component acts as a central module making decisions about fault tolerance strategies to be implemented by individual system components depending on the performance and energy requirements specified as system operating modes.

On structuring holistic fault tolerance

Traditional hierarchical modelling methods tend to have layers of abstraction corresponding to naturally existing layers of concern in multilevel systems. Although convenient, this is not always optimal for analysis and design. For instance, parts of a system which are in the same layer may not contribute to the same degree on some metric, e.g. system power consumption. To moderate the modelling, analysis and design effort, and potentially runtime control overhead for models used at runtime, less significant parts of the system should be studied at higher levels of abstraction and more significant ones with more detail. Concentrating on system power consumption, this paper presents Order Graphs (OGs), which have a clear hierarchical structure, but provide straightforward vertical zooming across multiple layers (orders) of model fidelity, resulting in the discovery of power-proportional cuts that run through different orders to be analysed together in a flat manner. Stochastic Activity Networks (SANs), a good flat modelling method, is suggested as an example of studying technique for cuts discovered with OGs. A series of experiments on an Odroid development system consisting of an ARM big.LITTLE multi-core structure provides initial validation for the approach. © 2015 Newcastle University. Printed and published by Newcastle University, Computing Science, Claremont Tower, Claremont Road, Newcastle upon Tyne, NE1 7RU, England. Bibliographical details RAFIEV, A., XIA, F., ILIASOV, A., GENSH, R., AALSAUD, A., ROMANOVSKY, A., YAKOVLEV, A. Power-proportional modelling fidelity [By] A. Rafiev, F. Xia, A. Iliasov, R. Gensh, A. Aalsaud, A. Romanovsky, A. Yakovlev Newcastle upon Tyne: Newcastle University: Computing Science, 2015. (Newcastle University, Computing Science, Technical Report Series, No. CS-TR-1443)

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Power-proportional modelling fidelity

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