A system for providing security to an in-vehicle communication network, the system comprising: a data monitoring and processing hub; and at least one module configured to monitor messages in communication traffic propagating in a vehicle's in-vehicle network, the network having a bus and at least one node connected to the bus, the module comprising: a communication interface configured to support communication with the hub; a memory having software comprising data characterizing messages that the at least one node transmits and receives during normal operation of the node; at least one communication port via which the module receives and transmits messages configured to be connected to a portion of the in-vehicle network; a processor that processes messages received via the port from the portion of the in-vehicle network responsive to the software in the memory to: identify an anomalous message in the received messages indicative of exposure of the in-vehicle network to damage from a cyber attack; determine an action to be taken by the module that affects the anomalous message; and transmit data responsive to the anomalous message to the hub for processing by the hub via the communication interface.

Global automotive safety system

An NFC-enabled electronic device and a method for operating the same are discussed. The method according to an embodiment includes performing, by the electronic device, tagging with a first external device to establish communication with the first external device; receiving, by the electronic device, at least one of device information and user information from the first external device through the communication; and transmitting, by the electronic device, a remote control signal to at least one second external device, based on the at least one of the device information and the user information.

Electronic device and method for operating the same

A memory system in embodiments includes a nonvolatile semiconductor memory that stores user data, a forward lookup address translation table and a reverse lookup address translation table, and a controller. The controller is configured to determine that the user data stored in the nonvolatile semiconductor memory is valid or invalid based on these two tables. The controller may perform data organizing of selecting data determined valid and rewriting the data in a new block. The controller may perform write processing and rewriting processing to the new block alternately at a predetermined ratio. The controller may determine whether a predetermined condition is satisfied on a basis of addresses included in write requests and write data in the MLC mode when the condition is satisfied and write data in the SLC mode when the condition is not satisfied.

Memory system and control method of memory system

A data processing system enables global shared memory (GSM) operations across multiple nodes with a distributed EA-to-RA mapping of physical memory. Each node has a host fabric interface (HFI), which includes HFI windows that are assigned to at most one locally-executing task of a parallel job. The tasks perform parallel job execution, but map only a portion of the effective addresses (EAs) of the global address space to the local, real memory of the task's respective node. The HFI window tags all outgoing GSM operations (of the local task) with the job ID, and embeds the target node and HFI window IDs of the node at which the EA is memory mapped. The HFI window also enables processing of received GSM operations with valid EAs that are homed to the local real memory of the receiving node, while preventing processing of other received operations without a valid EA-to-RA local mapping.

Host Fabric Interface (HFI) to Perform Global Shared Memory (GSM) Operations

Non-intrusive techniques have been developed to dynamically and selectively alter address translations performed by, or for, a processor (12). For example, in some embodiments, a memory management unit (16) is configured to map from effective addresses in respective effective (or virtual) address spaces to physical addresses in the memory, wherein the mappings performed by the memory management unit are based on address translation entries of an address translation table (9). For a subset of less than all processes, entry selection logic (81) selects from amongst plural alternative mappings coded in respective ones of the address translation entries. For at least some effective addresses mapped for a particular process of the subset, selection of a particular address translation entry is based on an externally sourced value. In some embodiments, only a subset of effective addresses mapped for the particular process are subject to dynamic runtime alteration of the address translation entry selection.

Processor and method for dynamic and selective alteration of address translation

A method includes providing an effective address, providing an address space identifier which identifies a currently executing process, providing a mapping modifier to form a modified address space identifier where the mapping modifier is based on at least one external signal generated outside the processor, using the effective address and the modified address space identifier to form a logical address, and providing a physical address corresponding to the logical address. When the effective address has a first effective address value, the address space identifier has a first address space identifier value, and the mapping modifier has a first mapping value, the physical address has a first physical address value. When the effective address has the first effective address value, the address space identifier has the first address space identifier value, and the mapping modifier has a second mapping value, the physical address has a second physical address value.

Non-intrusive address mapping having a modified address space identifier and circuitry therefor

In a processor having an address translation table, a method includes providing a logical address and control signal. When the control signal has a first value, a first physical address is provided corresponding to the logical address, and when the control signal has a second value, a second physical address is provided. The first physical address and the second physical address are stored in at least one valid entry of the address translation table. In one case, the first physical address is stored in a first valid entry having a tag field which matches the logical address and the second physical address is stored in a second valid entry having a tag field which matches the logical address. Alternatively, the first physical address is stored in a first field of a first valid entry and the second physical address is stored in a second field of the first valid entry.

Processor and method for altering address translation

The invention relates to an apparatus for transfer of data elements between a bus controller, such as a CPU, and a memory controller. An address translator is arranged to receive a write address from the CPU, to modify the write address and to send the modified write address to the memory controller. An ECC calculator is arranged to receive write input data associated with the write address, from the CPU, and to generate an error correction code on the basis of the write input data. A concatenator is arranged to receive the write input data from the CPU, and to receive the error correction code from the ECC calculator, and to concatenate the write input data and the error correction code to obtain write output data, and to send the write output data to the memory controller.

Apparatus for error detection in memory devices

A data bus network interface module for enabling reception and transmission of application messages to/from at least one host processing module of an integrated digital signal processing device via a data bus network is described. The data bus network interface module being arranged to receive at least one data bus message from at least one remote network node via the data bus network, read an identifier field of the received at least one data bus message, and make data content of the received at least one data bus message available to at least one debug module if the identifier field comprises an identifier value defined for debug use.

Data bus network interface module and method therefor

An interface including first and second transport protocol circuitry, a memory and a mode controller. The interface includes first and second physical interface types which are both selectively enabled to interface a set of pads. The first transport protocol circuitry is operative with the first type physical interface in a first mode and the second transport protocol circuitry is operative with the second type physical interface in a second mode. The memory stores a mode value indicative of the operating mode. The mode controller enables one of the physical interface types and a corresponding transport protocol based on the mode value. The first mode is the default mode, and the mode controller enables dynamic transition to the second mode. An escape indication may be enabled during the second mode for dynamic transition back to the first mode. Programmable timing values may be used to facilitate mode transitions.

Interface system and method with backward compatibility

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