Ranganathan Vasanth
Intel
48 Papers
138 Citations
Ranganathan Vasanth is an academic researcher from Intel. The author has contributed to research in topics: Cache & CPU cache. The author has an hindex of 7, co-authored 48 publications.
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Papers
Patent
Instructions and logic to perform floating-point and integer operations for machine learning
Himanshu Kaul,Mark A. Anders,Sanu Mathew,Anbang Yao,Ray Joydeep,Ping T. Tang,Michael S. Strickland,Xiaoming Chen,Tatiana Shpeisman,Appu Abhishek R,Koker Altug,Sinha Kamal,Balaji Vembu,Nicolas C. Galoppo Von Borries,Eriko Nurvitadhi,Rajkishore Barik,Tsung-Han Lin,Ranganathan Vasanth,Sanjeev Jahagirdar +18 more
- 18 Oct 2017
TL;DR: In this article, a graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture and a first compute unit included within the MPC, the at least one single instruction is required to cause the first unit to perform a two-dimensional matrix multiply and accumulate operation.
24
Patent
Efficient thread group scheduling
Ray Joydeep,Appu Abhishek R,Koker Altug,Sinha Kamal,Balaji Vembu,Rajkishore Barik,Eriko Nurvitadhi,Galoppo Von Borries Nicolas C,Tsung-Han Lin,Sanjeev Jahagirdar,Ranganathan Vasanth +10 more
- 11 Oct 2018
TL;DR: In this paper, a mechanism for intelligent thread scheduling at autonomous machines is described, which is based on detecting dependency information relating to a plurality of threads corresponding to a majority of workloads associated with tasks related to a processor including a graphics processor.
13
Patent
Coordination and increased utilization of graphics processors during inference
Appu Abhishek R,Koker Altug,John C. Weast,Mike B. MacPherson,Linda L. Hurd,Sara S. Baghsorkhi,Justin Gottschlich,Surti Prasoonkumar,Chandrasekaran Sakthivel,Liwei Ma,Elmoustapha Ould-Ahmed-Vall,Sinha Kamal,Ray Joydeep,Balaji Vembu,Sanjeev Jahagirdar,Ranganathan Vasanth,Dukhwan Kim +16 more
- 24 Apr 2017
TL;DR: In this article, a mechanism for facilitating inference coordination and processing utilization for machine learning at autonomous machines is described, which detects, at training time, information relating to one or more tasks to be performed according to a training dataset relating to a processor including a graphics processor.
13
Patent
Motion biased foveated renderer
Surti Prasoonkumar,Karthik Vaidyanathan,Atsuo Kuwahara,Hugues Labbe,Sameer Kp,Jonathan Kennedy,Ray Joydeep,Travis T. Schluessler,John H. Feit,Nikos Kaburlasos,Jacek Kwiatkowski,Tomer Bar-On,Carsten Benthin,Adam T. Lake,Ranganathan Vasanth,Appu Abhishek R +15 more
- 29 Oct 2018
TL;DR: In this paper, an embodiment of an electronic processing system may include an application processor, persistent storage media, a graphics subsystem, a sense engine, a focus engine, and a motion engine.
11
Patent
Method and apparatus for handling memory refresh and maintenance operations
Ranganathan Vasanth,Alankar Saxena +1 more
- 25 Apr 2002
TL;DR: In this article, the authors present a method and apparatus for handling memory refresh and maintenance operations for graphics and other applications, in particular, refresh and memory operations are executed in two stages.
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