R. Noble
Freescale Semiconductor
17 Papers
171 Citations
R. Noble is an academic researcher from Freescale Semiconductor. The author has contributed to research in topics: PMOS logic & Layer (electronics). The author has an hindex of 8, co-authored 17 publications.
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Papers
Patent
Semiconductor fabrication process including source/drain recessing and filling
Da Zhang,M. Jahanbani,Bich-Yen Nguyen,R. Noble +3 more
- 01 Dec 2004
TL;DR: In this paper, the NH4OH-based wet etch was used to fill the source/drain recesses and thereby create source and drain structures in a semiconductor fabrication process.
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Improved short channel device characteristics with stress relieved pre-oxide (SRPO) and a novel tantalum carbon alloy metal gate/HfO/sub 2/ stack
H.-H. Tseng,C. Capasso,James K. Schaeffer,E.A. Hebert,Philip J. Tobin,David C. Gilmer,Dina H. Triyoso,M. Ramon,S. Kalpat,E. Luckowski,W.J. Taylor,Y. Jeon,Olubunmi O. Adetutu,Rama I. Hegde,R. Noble,M. Jahanbani,C. El Chemali,B. E. White +17 more
- 13 Dec 2004
TL;DR: In this article, a novel stress relieved preoxide (SRPO) followed by ALD of HfO/sub 2/ reduces the local charge density near the gate edge and short channel threshold voltage instability.
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Embedded SiGe S/D PMOS on thin body SOI substrate with drive current enhancement
Da Zhang,Bich-Yen Nguyen,Ted R. White,Brian J. Goolsby,T. Nguyen,V. Dhandapani,J. Hildreth,M. Foisy,Vance H. Adams,Y. Shiho,Aaron Thean,David Theodore,M. Canonico,Stefan Zollner,S. Bagchi,S. Murphy,R. Rai,J. Jiang,M. Jahanbani,R. Noble,M. Zavala,R. Cotton,D. Eades,S. Parsons,P. Montgomery,A. P. Martínez,Brian A. Winstead,Michael A. Mendicino,Jon D. Cheek,J. Liu,Paul A. Grudowski,N. Ranami,P. Tomasini,Chantal J. Arena,C. Werkhoven,H. Kirby,C.H. Chang,C.T. Lin,H.C. Tuan,Y.C. See,S. Venkatesan,Venkat R. Kolagunta,N. Cave,J. Mogab +43 more
- 14 Jun 2005
TL;DR: In this article, the first time PMOS drive current enhancement with in-situ boron doped SiGe incorporation in recessed S/D regions for devices built on thin body SOI substrate was reported.
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Performance of super-critical strained-Si directly on insulator (SC-SSOI) CMOS based on high-performance PD-SOI technology
Aaron Thean,Ted R. White,Mariam Sadaka,Linda B. McCormick,M. Ramon,Rode R. Mora,P. Beckage,M. Canonico,X.-D. Wang,Stefan Zollner,S. Murphy,V. Van Der Pas,M. Zavala,R. Noble,Omar Zia,Laegu Kang,Venkat R. Kolagunta,N. Cave,Jon D. Cheek,Michael A. Mendicino,Bich-Yen Nguyen,Marius K. Orlowski,S. Venkatesan,J. Mogab,C.H. Chang,Yuan-Hung Chiu,H.C. Tuan,Y.C. See,Mong-Song Liang,Y.C. Sun,Ian Cayrefourcq,F. Metral,Mark Kennard,Carlos Mazure +33 more
- 14 Jun 2005
TL;DR: In this article, the performance of multiple-V/sub T/Triple-gate oxide SC-SSOI CMOS realized with Freescale's high-performance silicon-on-insulator (HiPerMOS-SOI) and SOITEC's advanced wafer-bonding technology is described.
28
Defect passivation with fluorine in a Ta/sub x/C/ high-K gate stack for enhanced device threshold voltage stability and performance
H.-H. Tseng,Philip J. Tobin,E.A. Hebert,S. Kalpat,M. Ramon,L. R. C. Fonseca,Z.X. Jiang,James K. Schaeffer,Rama I. Hegde,Dina H. Triyoso,David C. Gilmer,W.J. Taylor,C. Capasso,Olubunmi O. Adetutu,D. Sing,J. Conner,E. Luckowski,B.W. Chan,A. Haggag,S. Backer,R. Noble,M. Jahanbani,Y.H. Chili,Bruce E. White +23 more
- 05 Dec 2005
TL;DR: Using a novel fluorinated TaxCy/high-k gate stack, this article showed breakthrough device reliability and performance improvements, which is a critical result since threshold voltage instability may be a fundamental problem and performance degradation for high-k is a concern.
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