The impact of process variation on SRAM yield has become a serious concern in scaled technologies. In this paper, we propose a methodology to analyze the stability of an SRAM cell in the presence of random fluctuations in the device parameters. We provide a theoretical framework for characterizing the DC noise margin of a memory cell and develop models for estimating the cell failure probabilities during read and write operations. The proposed models are verified against extensive Monte-Carlo simulations and are shown to match well over the entire range of the distributions well beyond the 3-sigma extremes.

Statistical analysis of SRAM cell stability

The impact of process variation on SRAM yield has become a serious concern in scaled technologies. In this paper, we propose a methodology to analyze the stability of an SRAM cell in the presence of random fluctuations in the device parameters. First, we develop a theoretical framework for characterizing the dc noise margin of a memory cell. The framework is based on the concept that an SRAM cell is on the verge of instability when the gain across the loop formed by the cross-coupled inverters in the cell is unity. The noise margin criteria developed in this manner can be used to verify a cell stability in the presence of arbitrary DC noise offsets at the two storage nodes in the cell. We also develop metrics for estimating the cell stability during read and write operations and verify these models by extensive Monte Carlo simulations in a 65-nm CMOS process. Our results show that the proposed robustness metrics can be used to estimate cell failure probabilities in an efficient and accurate manner.

The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies

The POWER6trade microprocessor combines ultra-high frequency operation, aggressive power reduction, a highly scalable memory subsystem, and mainframe-like reliability, availability, and serviceability. The 341mm2 700M transistor dual-core microprocessor is fabricated in a 65nm SOI process with 10 levels of low-k copper interconnect. It operates at clock frequencies over 5GHz in high-performance applications, and consumes under 100W in power-sensitive applications.

Design of the Power6 Microprocessor

Fluctuation limitations on scaling CMOS SRAM cell transistor dimensions and operating voltages are demonstrated by measuring local stochastic distributions of 65-nm PDSOI CMOS SRAM cell storage node voltages during read, write, and retention modes of operation. These measurements reveal insights into terminal voltage dependencies of cell margin distributions - observations that are engaged to increase cell immunity to random VT fluctuations by several orders of magnitude by biasing the cell terminal voltages dynamically with a read-write asymmetry. Combinations of circuit techniques implementing these dynamic cell biasing schemes are demonstrated in a 9 kb times74 b PDSOI CMOS SRAM array with a conventional 65 nm SRAM cell and an ABIST. Measurements demonstrate these techniques to enable VMIN reductions of over 200 mV - lowering measured VMIN to 0.54 V and 0.38 V/0.50 V for single and dual VDD implementations, respectively. The techniques consume a 10%-12% overhead in area, impact performance marginally (<5%) and also enable over 50% reduction in cell leakage.

A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing

A simple analytical model that describes MOSFET operation in saturation from subthreshold to strong inversion is used to derive a new formulation of the intrinsic switching delay of the transistor. The proposed model follows the scaling trend of experimental ring-oscillator data better than the conventional CV/I metric. The historical trend of MOSFET performance scaling is examined, and it is shown that the continuous increase of the carrier velocity in the channel has been the main driver for the improved transistor performance with scaling. The dependence of velocity and mobility in recent strain-engineered devices is studied based on published experimental data, and a theory is proposed to justify this dependence. It is shown that the virtual-source velocity depends on low-field mobility more strongly than what was previously believed, in spite of the fact that state-of-the-art MOSFETs operate at 60%-65% of their ballistic limit. These observations will be used in Part II of this paper to explore the tradeoffs between key device parameters in order for the commensurate scaling of the device performance with its dimensional scaling to continue in the future high-performance CMOS generations.

MOSFET Performance Scaling—Part I: Historical Trends

A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL enhancement is shown to scale well to 65 nm with larger enhancement seen than at 90 nm design rules. A high performance 0.65/spl mu/m/sup 2/ SRAM cell is also presented. SOI allows the SRAM cell to use Metal 1 instead of Metal 2 for bit-line wiring, which lowers the capacitance and improves access times. A functional dual-core microprocessor test chip containing 76Mb SRAM cache and key execution units has been fabricated.

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

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High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell