The silicon pixel tracking system for the ATLAS experiment at the Large Hadron Collider is described and the performance requirements are summarized. Detailed descriptions of the pixel detector electronics and the silicon sensors are given. The design, fabrication, assembly and performance of the pixel detector modules are presented. Data obtained from test beams as well as studies using cosmic rays are also discussed.

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ATLAS pixel detector electronics and sensors

We review recent work done by the photonics packaging platform ePIXpack that serves the academic community with packaging and assembly developments in the area of integrated photonics. The paper includes recent examples of our packaging and assembly work, covering a broad range of technologies from silicon photonics to InP-based devices.

/pdf/packaging-and-assembly-for-integrated-photonics-a-review-of-1627cwemmj.pdf

Packaging and Assembly for Integrated Photonics—A Review of the ePIXpack Photonics Packaging Platform

3D-detectors, with electrodes penetrating through the entire substrates have drawn great interests for high energy physics and medical imaging applications. Since its introduction by C. Kenney et al in 1995, many laboratories have begun research on different 3D-detector structures to simplify and industrialise the fabrication process. SINTEF MiNaLab joined the 3D collaboration in 2006 and started the first 3D fabrication run in 2007. This is the first step in an effort to fabricate affordable 3D-detectors in small to medium size production volumes. The first run was fully completed in February 2008 and preliminary results are promising. Good p-n junction characteristics have been shown on selected devices at the chip level with a leakage current of less than 0.5 nA per pixel. Thus SINTEF is the second laboratory in the world after the Stanford Nanofabrication Facility that has succeeded in demonstrating full 3D-detectors with active edge. A full 3D-stacked detector system were formed by bump-bonding the detectors to the ATLAS readout electronics, and successful particle hit maps using an Am-241 source were recorded. Most modules, however, showed largely increased leakage currents after assembly, which is due to the active edge and p-spray acting as part of the total chip pn-junction and not as a depletion stop. This paper describes the first fabrication and the encountered processing issues. The preliminary measurements on both the individual detector chips and the integrated 3D-stacked modules are discussed. A new lot has now been started on p-type wafers, which offers a more robust configuration with the active edge acting as depletion stop instead of part of the pn-junction.

/pdf/first-fabrication-of-full-3d-detectors-at-sintef-1l4xghix07.pdf

First fabrication of full 3D-detectors at SINTEF

A novel all-in-polymer multichip module (MCM-P) process is presented for applications at D-band (110–170 GHz). The unique manufacturing approach is an additive 3-D printing approach based on a gradual photo-induced polymerization in the $z$ -direction with metallized interconnection layers in between. The package design integrates a broadband waveguide transition nearly covering the entire D-band. Different transmission-line types for chip interconnections were characterized up to 170 GHz. In prior research, a millimeter-wave monolithic integrated circuit (MMIC) amplifier using a 50-nm metamorphic high electron-mobility transistor technology was designed. In this study, the co-design with the package is presented. The amplifier MMIC was bond-wire free embedded in an MCM-P test structure and contacted with coplanar measurement probes. A gain of more than 20 dB within 100–170 GHz was measured. Based on those results, an amplifier MCM-P with integrated waveguide transitions of size 6 mm $\times$ 4.5 mm was developed. The MCM-P was surface mounted on a printed circuit board and flipped into a waveguide test fixture. A gain of more than 20 dB remained from 125 to 155 GHz with an input and output matching better than 10 dB.

Polymer Multichip Module Process Using 3-D Printing Technologies for D-Band Applications

In this paper, a high-resistivity silicon (HR-Si) interposer integrated with through-silicon via (TSV) electrically grounded coplanar waveguide (CPW) line is presented for 2.5-D/3-D heterogeneous integration of radio frequency (RF) microelectronics devices. In addition, design of TSV interconnection composed of two coaxial ladder-hollow-annular Cu (copper) TSVs of different diameters is utilized to maintain a sufficient freedom for strict standard cleaning to avoid Si resistivity degradation. The formation of the coaxial ladder TSV structure is more beneficial to the subsequent plating process because it reduces the aspect ratio of TSV vias. Hollow-annular Cu TSV is manufactured in order to reduce the problem of mismatch in coefficient of thermal expansion among TSV’s constituent materials. A layer of Au (aurum) film is utilized to passivate the exposed Cu surface of Si interposer. Au is widely used in III–V groups’ devices because of the good compatibility with photonic integrated circuits, conductivity, and corrosion resistance. HR-Si interposer with TSV grounded CPW line and test structure is fabricated and characterized. With the monitoring test results, it can be found that it changes little in the resistivity of Si substrate, though the whole process, which is a basic requirement for RF performance. RF property test results show that the insertion loss is about −0.20 dB/mm at 10 GHz for the presented TSV grounded CPW line and −0.02 dB per TSV. These test results are better than the traditional design. To verify its applicability to 2.5-D/3-D heterogeneous integration, RF microelectronics die is assembled on TSV interposer and tested, and the test results prove that it works properly.

Fabrication and RF Property Evaluation of High-Resistivity Si Interposer for 2.5-D/3-D Heterogeneous Integration of RF Devices

Much of the cost of manufacturing pixel detectors is due to bumping and flip chip assembly of the readout chips onto sensor tiles, even if it is done on wafer level. To address this issue, Fraunhofer IZM investigated two new technological approaches, namely screen printing using dry film resist and chip-to-wafer assembly. In the first approach, solder bumps with diameters of 80 and 25 μm in pitches of 110 and 60 μm, respectively, were produced by screen-printing solder paste using a photo-structured dry film resist. Results indicated that the technology is a viable high yield and low cost bumping process. The second approach was developed to decrease the number of manual handling steps in pixel module manufacturing, which is critical for reducing processing time and cost. Here, chip designs on 200 mm readout chip (ROC) wafers and 150 mm sensor wafers were especially adapted for chip-to-wafer assembly and to ensure that the interconnection yield and reliability could be tested. After bumping and dicing of the readout chip wafer and UBM plating on the sensor wafer, individual dice were flip chip mounted on the pre-diced sensor wafer. This paper describes the technological steps, key processing parameters and first results for both technologies.

Cost effective flip chip assembly and interconnection technologies for large area pixel sensor applications

About 1100 ATLAS bare modules will be assembled at Fraunhofer IZM. The bumping and assembly technology of these multichip-modules is described in this paper. Pixel contacts and lead–tin interconnection bumps are deposited by electroplating. A high yield manufacturing technology requires electrical test and optical inspection on wafer level as well as on chip level. In this paper, the result of optical inspection of more than 7600 readout chips is presented. Handling mistakes are the main reason for rejection of chips before flip chip assembly. A reliable process technology, the assembly of electrical Known Good Die (KGD), optical inspection after bumping and the development of a single chip repair technology result in 98% of good modules after flip chip assembly. The reliability of the bump interconnections was even checked by thermal cycling and accelerated thermal aging.

Experience in fabrication of multichip-modules for the ATLAS pixel detector

Packaging of semiconductor detector modules has been one of the most promising research projects at Fraunhofer IZM. The applications vary from X-ray detection for medical diagnostics to particle detection for fundamental physical research. Starting from feasibility studies a high yield manufacturing process has been established. In this paper the bumping and assembly technology of pixel detector modules is exemplified by the manufacturing of modules for the setup of the ATLAS pixel detector at the large hadron collider (LHC) at CERN, Geneva. The pixel contacts and the interconnection bumps are deposited by electroplating. Yield is one of the most important parameters for the implementation of multichip module (MCM) concepts. Therefore a high yield manufacturing technology requires consistent electrical test and optical inspection on wafer level as well as on chip level running in parallel to the production process. A total module yield of 98% for packaging of 1000 MCMs each having 16 flip-chips has been achieved. Further examples of pixel detectors packaged at Fraunhofer IZM are presented in this paper. These are complex particle detector prototypes with diamond sensor material and pixel detector modules for X-ray imaging. The different amount of readout chips assembled on one sensor substrate and the amount of modules for the assembly of the whole detector require different manufacture technologies from single chip processing up to processing on wafer level.

Packaging of radiation and particle detectors

The trend towards smaller, lighter and thinner products requires a steady miniaturization which has brought-up the concept of Chip Scale Packaging (CSP). The next step to reduce packaging cost was the chip packaging directly on the wafer. Wafer Level Packaging (WLP) enables the FC assembly on PWB without interposers. New and improved microelectronic systems require significant more complex devices which could limit the performance due to the wiring of the subsystems on the board. 3-D packaging using the existing WLP infrastructure is one of the most promising approaches. Stacking of chips for chip-on-chip packages can be done by wafer-to-wafer stacking or by chip-to-wafer stacking which is preferable for yield and die size considerations. This chip-on-chip packaging requires a base die with redistribution traces to match the I/O layout of both dice. This allows the combination of the performance advantage of flip chip with the options of WLP. To avoid the flip chip bonding process the thin chip integration (TCI) concept can be used. Key elements of this approach are extremely thin ICs (down to 20 μm thickness) which are incorporated into the redistribution. This technology offers excellent electrical properties of the whole microelectronic system. The focus of this paper will be the technology requirements for the realization of different kinds of chip-onchip packages.

Technology Requirements for Chip-On-Chip Packaging Solutions

The PARADIGM (Photonic Advanced ResearchAnd Development for Integrated Generic Manufacturing) European Union Project focuses on design and fabrication ofcomplex photonic integrated circuits (PICs) at low cost. A partof the project was to design a generic package for diverse PICs, and a co-planar waveguide with through silicon vias (TSV) wasa requirement therefor. The through silicon vias shouldimprove the high frequency performance of the waveguide dueto better distribution of the ground level over the wholedevice. As conduction material inside the TSVs copper is a well-known and commonly used material. However copperbeing a well-known source of degradation in III-Vsemiconductors a copper free metallization system had to bedeveloped. Gold is widely used in III-V devices to formcontacts and should therefore be used as conduction materialfor the TSVs and the contacts on top of the device. Ametallisation system based on gold was developed successfully. The TSVs had a diameter of 200 µm and were 400 µm deep(Aspect Ratio: 2). The co-planar waveguide and the TSVs werefabricated on 100mm wafers at Fraunhofer IZM using waferlevel-thin film technology. A reference sample without anyTSV was fabricated as well. The diced samples with andwithout TSVs were electrically tested at CIP and evaluatedwith respect to their high frequency performance (0 -- 40 GHz). Crosstalk and bandwidth (Bandwidths > 40 GHz wereobserved for a 10 mm long track) showed significantly betterperformance when TSVs were utilised in the device.

Gold TSVs (Through Silicon Vias) for High-Frequency III-V Semiconductor Applications

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