A system for real-time digital signal processing employs a single-chip microcomputer device (10) having separate on-chip program ROM (14) and data RAM (15), with separate address and data paths for program and data. An external program address bus (RA) allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus (D). A bus interchange module (BIM) allows transfer between the separate internal program and data busses (P-Bus and D-Bus) in special circumstances. The internal busses are 16-bit, while the ALU and accumulator (Acc) are 32-bit. A multiplier circuit (M) produces a single state 16 x 16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0- to 15-bit shifter (S) with sign extension.

Microcomputer system for digital signal processing

A timing system, for distributing clock signals in a synchronous processing system having plural processing sections, includes a central clock circuit and a plurality of section clock circuits, each section clock circuit being located in and associated with a different one of the processing sections. Each section clock circuit is arranged to respond to a system clock signal for stepping through a plurality of states including a state common to the plurality of section clock circuits. An arrangement, responsive to the system clock signal, produces and transmits to the plurality of section clock circuits a synchronization signal that routinely sets the plurality of section clock circuits to the common state. The timing system may further include an arrangement for controlling suspension of processing in the plural processing sections.

Distributed timing system

A single-chip, software-programmable digital signal processor, intended for telecommunication applications, has been developed. The processor, fabricated with the most advanced 3 /spl mu/m n-channel E/D MOS technology, incorporates a 16/spl times/16-bit full hardware multiplier and a sophisticated bus structure to minimize bus conflicts, thus attaining the capability to implement 55 second-order filters at a sampling rate of 8 kHz with sufficient dynamic range to process PCM encoded signals. The authors describe the design concept, architecture, instructions, device design, and application techniques.

A single-chip digital signal processor for telecommunication applications

This correspondence examines integrated-circuit logarithmic arithmetic units which include adders, subtracters, multipliers, and dividers. The design of these arithmetic units is reviewed, and an example arithmetic unit which performs multiplication followed by addition is designed in detail. The design results are used to develop a size and speed comparison of integrated-circuit logarithmic and fixed-point arithmetic units. This comparison is exercised through a video signal processing example. It is concluded from this comparison that logarithmic arithmetic units are smaller than, and as fast as, fixed-point arithmetic units with comparable capabilities in digital signal processing applications characterized by large dynamic range and moderate computational accuracy requirements. Further, this comparison quantitatively illustrates the interaction of digital-signal-processing and integrated-circuit issues in the design of special-purpose digital signal processors.

Integrated-Circuit Logarithmic Arithmetic Units

A data control circuit (18) for an input/output arrangement is arranged for controlling the transfer of a data word through a shift register (20 or 120) to or from a peripheral device (22 or 122). The circuit (18) provides for selection between internal clock generation at one of several rates or application of an external clock and for selection of the length and format of the data words to be transferred. Selection is accomplished by an interval counter (38), format data stored in a control register (37), two gating circuits (30 and 40) and a selection circuit (35).

Data control circuit

This paper will report on a programmable digital signal processor chip which can decode on instruction, fetch data, perform a 16 × 20b multiply, and add the resultant to a 40b accumulator in 80ns. Circuit permits all signal processing functions of a dual-tone multifrequency receiver or a low-speed modem to be realized on one chip.

A digital signal processor for telecommunications applications

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A digital signal processor for telecommunications applications