Embodiments described herein include a quadrature phase corrector (QPC) which includes multiple differential amplifies for correcting the phase of one or more clock signals. In one embodiment, the differential amplifiers are arranged in an input stage, cross-coupled stage, and ring stage. The input stage receives and buffers the input clock signal (or signals). The cross-coupled stage includes one or more latches that force one clock signal high and another low which causes the QPC to oscillate. The ring stage outputs four clock signals with adjusted phases relative to the input clock signals. In one example, the ring stage outputs a quadrature clock signal that includes four clock signals phase shifted by 90 degrees.

Open-loop quadrature clock corrector and generator

This paper presents a source-synchronous receiver architecture for use in parallel optical links. The proposed system is reconfigurable, allowing any channel to be used as a clock or data lane. The architecture is designed for mode-division multiplexed (MDM) optical links with forwarded clocks and allows the sensitive clock signal to be placed in the lane with the least amount of optical crosstalk for a given photonic interconnect. This configurability, which accounts for variation in integrated optics by leveraging the more robust electronic chip, optimizes the performance in electronic/optic codesigned solutions and may improve the yield. The architecture contains a dynamic clock distribution network, able to send a reference clock signal from the chosen clock receiver to any other data-configured receiver. The proposed architecture has been implemented on an experimental chip consisting of two receivers designed in the 65-nm CMOS technology. Electrical measurements at 8 Gb/s were done, and bit error rate curves are presented. They demonstrate the ability to swap and repurpose the clock and data inputs between the receivers, with similar sensitivity upon reconfiguration as a proof of concept.

Reconfiguration in Source-Synchronous Receivers for Short-Reach Parallel Optical Links

The purpose of this work is, to introduce design of a 32-bit MIPS (Million Instruction Per Second) based CPU containing five stages of the pipeline, to incorporate power optimization techniques for the processor. The functionality of design is verified by writing Verilog Modules on Xilinx 14.5 choosing the target FPGA device. Synthesis and simulation results have been taken from ModelSim 6.2c. Analysis of the design floorplan of 32-bit CPU and study of the detailed netlist has been achieved on PlanAhead tool, which was giving accurate results. From the performance viewpoint, FPGA-based implementation of processor is totally centered on the designing of processor architectures in Verilog HDL and increasing the overall speedup with power mitigation at Spartan class (45nm and 90nm) FPGAs. The significant features of this work are; increased number of instructions, enhanced performance and low power consumption with HDL modification techniques. The design has consumed less than 119mW of power with the maximum frequency of operation at 70.413MHz for Spartan-6. Optimized power observed was about 22.72% after applying power reduction techniques, which make this work useful for low power FPGAs.

Power mitigation in high-performance 32-bit MIPS-based CPU on Xilinx FPGAs

A quadrature clock generator is disclosed. The quadrature clock generator may include a first injection-locked oscillator, a phase interpolator, and a second injection-locked oscillator. The first injection-locked oscillator may generate a first plurality clock signals from a first reference clock signal. The phase interpolator may generate a second reference clock signal from the first plurality of clock signals, and the second injection-locked oscillator may generate a second plurality of clock signals from the second reference clock signal. A first quadrature clock signal may be selected from the first plurality of clock signals and a second quadrature clock signal may be selected from the second plurality of reference clock signals.

Low noise quadrature signal generation

To achieve better performance, computer designers employ advanced techniques that shrink feature sizes, lower supply voltage, increase clock rates and memory capacity, and meanwhile modern computers become increasingly vulnerable to soft errors caused by energetic particles, such as alpha particles and neutron strikes. Therefore, fault tolerance evolves into one of the most significant design objectives, especially for embedded systems working under extreme environments, such as space project. Techniques both in hardware and software are presented. Most of these techniques, however, either require extra resources (e.g. redundant component) or cause great performance degradation. In this paper, we propose a novel fault tolerant technique for Java Virtual Machine (JVM) called the warm-JVM rejuvenation, which can proactively correct soft errors. This approach periodically performs JVM rejuvenation during the execution of Java applications. The experiments show that our approach can improve the JVM reliability and maintain performance and response time.

A Fault-Tolerant Java Virtual Machine Using Fast Rejuvenation for Soft-Error-Prone Systems

This paper presents an energy-efficient forwarded-clock receiver in 40nm CMOS process. The receiver adopts injection-locked ring oscillator (ILRO) to implement jitter filtering and phase deskew. The proposed cascaded ILROs enable our receiver to maintain a constant jitter tracking bandwidth (JTB) for good jitter tolerance and generate accurate quadrature clocks for quarter-rate sampling. The first-stage ILRO is used to control the JTB and filter out the high-frequency clock jitter that cannot track the data jitter. The second-stage ILRO is injected by the first one's outputs to generate precise quadrature clocks for phase shifting and deskew. The simulation results show our receiver can work at 8Gb/s and consume only 6mW under a 0.9V power supply voltage. The JTB can be controlled up to 260 MHz with a variation less than 20 MHz and the quadrature phase error is minimized to 1°.

An 8Gb/s 0.75mW/Gb/s injection-locked receiver with constant jitter tracking bandwidth and accurate quadrature clock generation in 40nm CMOS

A 64-bit RISC processor is designed for large applications that need large memory address. Due to the restriction of the instruction fixed length, loading a 64-bit address needs a number of instructions, leading to a penalty both of memory performance and memory consumption. This paper describes an address computation method based on hardware and software co-design. In our extended MIPS processor which supports register + register addressing, we achieve an approximate effect of memory access as their 32-bit counterparts, we propose a software load-address method, which simplifies the calculation of 64-bit address. We implement our methods in the 64-bit Open JDK 6 on MIPS, and give both performance and consumption comparisons for SPECjvm2008 and Dacapo. The experimental results show that the performance of SPECjvm2008 is improved by 5.1%, the performance of Dacapo is improved by 7.3% and near to 24% for some benchmarks. The size of method generated by JVM compiler is reduced by an average of 13%.

Optimizing Memory Access with Fast Address Computation on a MIPS Architecture

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An 8Gb/s 0.75mW/Gb/s injection-locked receiver with constant jitter tracking bandwidth and accurate quadrature clock generation in 40nm CMOS

Optimizing Memory Access with Fast Address Computation on a MIPS Architecture