In the present study, diopside nanopowders were prepared via mechanical milling with eggshell as the calcium source. The space holder method (compaction of ceramic powder and spacer) as one of the most important methods to produce ceramic/metal scaffolds was used to produce diopside scaffolds. For the first time, the effect of the spacer size on mechanical properties and porosity of the obtained scaffolds was experimentally discussed. According to the results obtained, the NaCl particles (as the spacer) with the size of 400–600 µm maintained their original spherical shape during the compaction and sintering processes. As a new work, the most important parameters including the spacer type, spacer concentration, spacer size, and applied pressure were considered, and their effects on mechanical properties and porosity of diopside scaffolds were simulated. Gene Expression Programming (GEP), as one of the most branches of the artificial intelligence, was used for simulation process. By using the GEP, two equations were introduced to predict the compressive strength and porosity of the obtained scaffolds with the lowest error values. The 3D diagrams extracted from the model were used to evaluate the combined effect of the process parameters on the compressive strength and porosity of the scaffolds. The GEP model presented in this work has a very low level of error and a high level of the squared regression for predicting the compressive strength and porosity of diopside scaffolds.

Preparing diopside nanoparticle scaffolds via space holder method: Simulation of the compressive strength and porosity.

This paper outlines low power nano-scale circuit design for even parity generator, as well as, even parity checker circuit using quantum-dot cellular automata (QCA). The proposed even parity generator and even parity checker are achieved by using a new layout of XOR gate. This new XOR gate as a state-of-the-art is much denser and faster than the existing ones. The proposed parity generator has outshined the existing design by reducing the cell count as 10%, area as 5.66%, and latency by 12.5%. The proposed parity checker has also outshined the existing design with an improvement in cell count as 17.94% and in the area as 38.46% having a reduction in latency of 22.22%. The comparison proves that the circuits are denser and faster than the existing one. Nano communication architecture with the proposed circuits also demonstrates the efficiency of this design. Furthermore, the bit-error coverage by the proposed method is described. Besides, the defects in the circuits are explored to facilitate guide to proper implementation. The tests vectors are proposed to identify the defects in the designs and the defect coverage by those test vectors. The estimation of dissipated energy by the layouts establishes a very low energy dissipation nature of the designs. Different parameters like a logic gate, density, and latency are utilized to evaluate the proposed designs that confirm the faster processing speed at nano-scale.

/pdf/qca-based-error-detection-circuit-for-nano-communication-4h6rtjcqfn.pdf

QCA Based Error Detection Circuit for Nano Communication Network

A new efficient design for random access memory based on quantum dot cellular automata nanotechnology

Quantum dot cellular automata (QCA) are pledging nanotechnology which has been used widely in digital circuits and systems. Conventional lithography based VLSI model encounter acute challenges of tunneling, variation of doping and short channel issue. In a remarkably fast development of VLSI technology, it is the cardinal of the age to reach a stable model with area and low power consumption. QCA is a promising alternative to complementary metal–oxide–semiconductor (CMOS) technology with many enticing features such as high-speed, low power consumption and higher switching frequency than transistor based technology. The code converters are the basic unit for transformation of data to execute arithmetic processes. In this paper, a novel QCA based 2-bit binary-togray, 3-bit binary-to-gray, and 4-bit binary-to-gray code converter have been proposed. The proposed design reduces the number of cells, area, and raises switching speed. The energy dissipation by the proposed circuits are evaluated which certifies the prospect of QCA nano-circuit presenting as a substitute level for the attainment of reversible circuits. The consistency of the proposed circuits is tested under thermal randomness that reveal the functioning effectiveness of the circuits. The proposed circuits are simulated using QCADesigner and Microwindlite tool which is widely used for simulation and verification.

http://www.sersc.org/journals/IJMUE/vol11_no8_2016/38.pdf

Novel Binary to Gray Code Converters in QCA with Power Dissipation Analysis

Quantum dot cellular automaton (QCA) are dominant nanotechnology which has been used extensively in digital circuits and systems. It is a promising alternative to complementary metal–oxide–semiconductor (CMOS) technology with many enticing features such as high-speed, low power consumption and higher switching frequency than transistor based technology. The code converters are the basic unit for transformation of data to execute arithmetic processes. In this paper, QCA based 2-bit binary-to- gray; 3-bit binary-to-gray and 4-bit binary-to-gray code converter have been proposed. The proposed design reduces the number of cells, area and raises switching speed. The simulations are completed using QCADesigner and Microwindlite tool which is widely used for simulation and verification.

/pdf/implementation-of-binary-to-gray-code-converters-in-quantum-12cs891wmn.pdf

Implementation of Binary to Gray Code Converters in Quantum Dot Cellular Automata

QCA technology is a possible substitution for semiconductor-based technology. This paper presents a novel design of a Quantum-dot Cellular Automata (QCA) Peres Gate (PG) and its simulation. Peres Gate (PG) is a reversible logic gates. Reversible logic gates are attracting a lot of attention due to their zero power dissipation under ideal conditions. Reversible logic circuits are useful for constructing quantum computers.

https://eujournal.org/index.php/esj/article/download/3844/3683

A novel presentation of peres gate (pg) in quantum-dot cellular automata(qca)

http://www.sersc.org/journals/IJGDC/vol10_no5/2.pdf

An Efficient Design of Reversible Subtractor in Quantum-Dot Cellular Automata

Reversible computing in Quantum-dot Cellular Automata (QCA) is an expanding research field at ultra low power nano-computing area. Utilization of minimum power, rapid momentum, advanced switch in grate and scale arrangement of QCA assurances cost operative proficient logic outline with extreme intricacy at nano-scale. In this article two fundamental reversible logic gates, Feynman and Toffoli gate are presented. In contrast with earlier QCA layouts, the proposed designs are achieved with the lowest number of QCA cells, minimal extent and clock delay exclusive of any wire-crossing approaches. Moreover, the proposed circuits have been verified and simulated using QCADesigner and QCAPro has been employed to estimate the power dissipation.

Efficient Design of Feynman and Toffoli Gate in Quantum dot Cellular Automata (QCA) with Energy Dissipation Analysis

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A novel presentation of peres gate (pg) in quantum-dot cellular automata(qca)

An Efficient Design of Reversible Subtractor in Quantum-Dot Cellular Automata

Efficient Design of Feynman and Toffoli Gate in Quantum dot Cellular Automata (QCA) with Energy Dissipation Analysis