Ternary Logic Circuits have gained the crucial attention of all the semiconductor researchers as it provides better interconnect, power, performance and speed when compared to the conventional binary logics. There is a minimal area overhead in ternary logics but that’s permissible as long as other parameters provide a much beneficial results. Carbon Nano Tube (CNT) Transistors are a remarkable replacement for the conventional Complementary Metal Oxide Semiconductors (CMOS) as they exhibit better electrical connectivity, structural abilities and mechanical properties. The main focus of present-day requirements are designing and developing power optimized high speed circuits without compromising on performance and area. So, to achieve all these, this research work focus on combining both the high-profile techniques to build Low Powered Ternary Arithmetic Logic Circuits (LP- TALCs) using CNT transistors. ALCs plays the major role as the basic operating unit for any processors or circuits which helps to perform arithmetic operations and logic operations in single structure. The various logic operations performed by this TALC circuit is Buffer, Inversion, Ternary NAND, Ternary NOR, Ternary AND, Ternary OR, Ternary Adder, Ternary Subtractor and Ternary Comparator. The structure basically consists of Low Power Enabled Decoder (LPED), Functional modules and Output selection circuit (OSC). LPED circuit helps to achieve low power by enabling the selected circuit operations using decoder circuits and the inputs are fed to functional modules which consists of all the logical structure and finally the output selection circuit consists of encoders which deliver the final output function. The proposed structure is designed using 32nm CNTFET technology and the simulation results shows almost 90% power reduction to their binary counterpart and 85% Power delay product improvement. 

Power Optimized Ternary Arithmetic Logic Circuit using Carbon Nano Tube Field Effect Transistor

Present study unfolds a new optimized scalable circuit topology to generate the 3’s complement of a base-3 input and the corresponding 2-step design strategy with respect to an illustrative 4-trit 3’s complement generator is elaborated. A novel idea at step-l generates the 2’s complement of a ternary-input. Next, in step-2 the ternary ‘‘1’’ is added with the 2’s complement result from step-l in order to generate the 3’s complement output. The clever hardware optimization strategy applying possible fixed-input to the circuit (wherever applicable) is adopted here for the purpose. The complete 4-trit 3’s complement generator is designed on 32nm standard CMOS technology using BSIM4 model parameters with 0. 9V supply-rail at 27°C temperature using SEdit of Tanner EDA. The extensive T-Spice transient simulations with all possible test patterns validate the circuit operation. As per evaluation the proposed circuit produces output with S3.37ps propagation delay, 175.65$\mu$W averagepower and 14.64× 1$0^{-15}$J PDP when operated with 100MHz ternary input. 

Novel 32nm CMOS Ternary 3‘s Complement Generator

This paper unfolds a new speed-power efficient single-step design to hardware-encrypt-decrypt original-message in a binary format with a block-wise ternary-operator to achieve secured end-to-end-communication, hiding confidential information from third-party intervention. The scheme can be integrated as cryptographic hardware primitive cells with IoT/portable devices. The proposed T-Encryptor operates in a single step on a 4-bit binary input block at a time, to produce corresponding 3-trit encrypted ternary output. Encryption is done by taking 2’s complement of the original binary message and converting it to ternary. Reverse steps are followed at the receiving end. A novel design that consists of 2:1-binary and 3:1 ternary multiplexer modules along with a clever pass-transistor input-switching network, implements the proposed T-Encryptor/Decryptor on conventional MOS. The Design and optimization of the proposed T-Encryptor/Decryptor are done on the BSIM4 device parameter using the 32nm-standard-CMOS Technology at 0.9 V supply-rail at 27°C. Bits “0” and “1” are denoted by 0 and 0.9 V, respectively, whereas ternary digits “0”, “1” and “2” are denoted by 0, 0.45 and 0.9 V, respectively. The transient response of the proposed design is validated by extensive T-Spice simulations. 

Novel Single-Step 32nm-CMOS Hardware T-Encryptor/Decryptor

Present study unfolds a new optimized scalable circuit topology to generate the 3’s complement of a base-3 input and the corresponding 2-step design strategy with respect to an illustrative 4-trit 3’s complement generator is elaborated. A novel idea at step-l generates the 2’s complement of a ternary-input. Next, in step-2 the ternary ‘‘1’’ is added with the 2’s complement result from step-l in order to generate the 3’s complement output. The clever hardware optimization strategy applying possible fixed-input to the circuit (wherever applicable) is adopted here for the purpose. The complete 4-trit 3’s complement generator is designed on 32nm standard CMOS technology using BSIM4 model parameters with 0. 9V supply-rail at 27°C temperature using SEdit of Tanner EDA. The extensive T-Spice transient simulations with all possible test patterns validate the circuit operation. As per evaluation the proposed circuit produces output with S3.37ps propagation delay, 175.65$\mu$W averagepower and 14.64× 1$0^{-15}$J PDP when operated with 100MHz ternary input.

Identifying the middle value "1" of a ternary digit (trit) among 3-valued symbols "0", "1" and "2" is a major factor in most of the Ternary-based system design This paper explores the circuit concept with working principle that can distinguish trit value "1" from others The complete circuit has been designed on TSMC 90nm CMOS technology using BSIM4 device parameters with 10V supply rail at 27°C temperature Ternary-digits "0", "1" and "2" are denoted by 0V, 05V and 10V respectively The designed circuit has been validated through extensive T-Spice simulations with all possible test patterns using PWL data source As per T-Spice simulation results the designed circuit dissipates 2202µW average power with 022ns propagation delay

Ternary Middle Value Decoder (T-MVD) on 90nm CMOS Technology

Present study explores a new circuit topology for parity-based error detection in ternary domain. Proposed concept is discussed and applied to construct 4-trit Ternary even as well as odd parity generator-checker using conventional Enhancement-type Metal Oxide Semiconductor (MOS) transistor. Proposed idea adds two more redundant trit with the original ternary input sequence (i.e., one is for trit “1” and another is for trit “2”) to generate/check corresponding parity output. The complete circuit is designed on 32nm standard CMOS technology considering BSIM4 device model parameters with 1.0V supply rail at 27°C temperature. The ternary digits “0”, “1” and “2” are represented with 0V, 0.5V and 1.0V respectively. The extensive T-Spice transient simulations with all possible test patterns validate the proposed design. Ternary input for the simulation is applied using Piece-Wise-Linear (PWL) input source. Circuit speed-power response is evaluated and recorded.

Novel 32nm CMOS Ternary Parity Generator-Checker

AbstractA new full-custom design of Unary-to-Ternary-Encoder (UTE) using standard Enhancement-Type-Metal–Oxide-Semiconductor-Field-Effect-Transistor reporting low-PDP (Power-Delay-Product) and low-area is presented. The inherent pass characteristic of the E-MOS-transistor is exploited here to develop the proposed Ternary-Encoder. Theoretical aspects along with the operation of proposed 9:2 and 27:3 UTE are discussed. The complete UTE is designed and optimized on 32 nm standard CMOS technology at 0.9 V supply-rail and 27°C. Ternary digits “0”, “1” and “2” are represented with 0 V, 0.45 V and 0.9 V respectively. The proposed design is validated through extensive T-Spice front-end transient simulations with all possible test patterns. The layout of the proposed design is completed on 32 nm Single-Poly-Double-Metal (SPDM) CMOS--Technology. After DRC and LVS post-layout simulation with extracted parasitic and 1 fF load, is carried out. The valuated performance of the 9:2 UTE is next compared with a recent candidate design to this end, from open literature to benchmark. The Power-Delay-Product (PDP) of proposed UTE is measured by applying ±10% supply variation from nominal on slow, typical and fast MOSFET at −40°C, 27°C and 85°C. Finally, the speed-power characteristic of the proposed 9:2 UTE is explored under different load conditions from 1 to 10 fF.Keywords: E-MOS pass characteristic; Encoding scheme; PDP (Power delay product); PVT (Process-voltage-temperature) analyses; Transient analyses; Ternary system Disclosure statementNo potential conflict of interest was reported by the author(s).Additional informationNotes on contributorsAloke SahaAloke Saha (M’15) received Btech degree in EIE from Kalyani University, India in 2003, ME degree in ECE (Instr. & Control) and PhD in Engineering from BIT Mesra, India in 2006 and 2015 respectively. He was associated with ECE Department of BIT Mesra as a Lecturer from 2006 to 2009. Presently he is an assistant professor of electronics and communication engineering (ECE) at Dr B. C. Roy Engineering College, Durgapur, India. Dr Saha is a reviewer for several SCI/ESCI/Scopus Indexed Technical Journals and has published a number of good-quality research papers. His area of interest includes cut-in age efficient digital computing, ternary and/or double base system development, encryption/decryption strategy, bio-medical signal processing, scalable architecture with adaptive control, floating point circuit/system etc. Email: saha81@gmail.comPrerona SanyalPrerona Sanyal was born in Asansol, India in the year of July 1991. Ms P. Sanyal completed her diploma in electronics and telecommunication engineering from “The New Horizon Institute of Technology”, Durgapur, India in the year 2015. She received her Btech in electronics and communication engineering and Mtech in modern communication engineering (ECE) from Dr B. C. Roy Engineering College, Durgapur, India in the years 2018 and 2020 respectively. Her current research interest includes data security, circuit-optimization, ternary system etc. Email: prernasanyal@gmail.comDeep Narayan SinghDeep Narayan Singh was born in Varanasi, India in the year of October 1994. Mr Deep Narayan Singh received her diploma in electrical and electronics engineering from “Xavier Institute of Polytechnic and Technology”, Ranchi and pursuing a Btech in electronics and communication engineering from Dr B. C. Roy Engineering College, Durgapur, India in the year of 2019 and 2022 respectively. His current research interest includes VLSI system optimization, parallel processing, low-power system design etc. Email: deepxipt@gmail.comAastha BhartiAastha Bharti was born in Deoghar, Jharkhand, India in the year of March 2001. Ms A. Bharti is pursuing her Btech in electronics and communication engineering from Dr B. C. Roy Engineering College, Durgapur. Her current research interest includes microelectronics circuits/systems, signal processing, number systems. Email: aasthabharti1003@gmail.comDipankar PalDipankar Pal (M’1999–SM’2008) was born in Chandannagar, India, in 1961. He received his Btech degree in electrical engineering from the Indian Institute of Technology, Delhi, India, in 1984 and his PhD. degree in electronics and telecommunication engineering from Jadavpur University, Calcutta, India, in 1997. In 2002, he was a Royal Society Visiting Fellow at the University College London (UCL), London, U.K. From 2003 to 2005, he was an EPSRC Research Fellow at the University of Bath, Bath, U.K. From 2007 to 2008 he was a Visiting Fellow at UCL. He was also a professor of microelectronics at the Birla Institute of Technology (BIT), Mesra, India, where he headed the microelectronics and VLSI research group within the department of electronics and communication engineering. From 2011 to 2014 he served as the Director of the North Eastern Regional Institute of Science & Technology (NERIST), a deemed university under MHRD, Government of India. Currently, he is a professor of microelectronics in the department of electrical & electronics engineering at BITS Pilani, K. K. Birla Goa-Campus, India. He has published over 60 articles in peer-reviewed journals and international conference proceedings. His research area includes microelectronics, digital and analog circuits and systems, and analog ASIC. Dr Pal is a Fellow of the Institution of Engineers (India). Corresponding author. Email: dipankarp@goa.bits-pilani.ac.in 

Speed-Power Efficient Novel CMOS Unary-to-Ternary Encoder

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Ternary Middle Value Decoder (T-MVD) on 90nm CMOS Technology

Novel Single-Step 32nm-CMOS Hardware T-Encryptor/Decryptor

Novel 32nm CMOS Ternary Parity Generator-Checker

Speed-Power Efficient Novel CMOS Unary-to-Ternary Encoder