The high-performance server compute landscape is changing. The traditional model of building general-purpose enterprise compute boxes that end-users can configure with storage and networking to assemble their desired compute environments, has evolved to purpose-built systems optimized for specific applications. This tight integration of hardware and software components together with high-density midboard optical modules and an optical backplane allows for unprecedented levels of switching and compute efficiencies and has fueled the penetration of optical interconnects deep “inside the box,” particularly for switch scale-up. We briefly review earlier 40 G/port switching systems based on active optical cables, and present our newest system: An all-optically-interconnected 100 G/port 8.2 Tb/s InfiniBand packet switch ASIC with 41 ports running 100 Gb/s per port interconnected by 12-channel midboard optical transceivers with 25 Gb/s per channel per direction of optical I/O. Using a blind-mate optical backplane, these components enable systems with up to 50 Tb/s bandwidth in a 2U standard rack mount configuration with industry-leading density, efficiency, and latency. For even tighter co-integration of optical interconnects with switch and processor ASICs, we discuss photonic multichip module and interposer packaging technologies that will further improve system energy efficiencies and overcome impending system I/O bottlenecks.

From Chip to Cloud: Optical Interconnects in Engineered Systems

In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

Always-on audio control for mobile device

In accordance with an embodiment, a method of calibrating a circuit includes coupling a first reference voltage to a first input of the circuit, coupling a programmable reference voltage to a reference node of a digital-to-analog converter (DAC), such that the gain of the DAC is dependent on an input value at the reference node. The method further includes providing a first predetermined input code to the DAC, summing an output of the DAC with the first reference voltage to produce a summed output, comparing the summed output to a threshold, and adjusting the programmable reference voltage until the summed output is within a predetermined range of the threshold.

System and method for calibrating a circuit

We present a novel 3.3- $\mu \text{m}$ radius ring modulator design with dramatically reduced resonance wavelength variations. By implementing a multi-mode waveguide design for the ring waveguides, phase errors from processing non-idealities in waveguide width and etching depth are significantly reduced. Measured resonance wavelengths from four 200-mm wafers fabricated in a commercial 130-nm CMOS foundry showed a total of $\sim 5$ -nm peak-to-peak variation, which is only about 1/6 of the free spectral range of the ring design. With this tighter control over the absolute resonance positions, the tuning range and tuning power requirements of the ring modulators can be significantly reduced, which in turn enhances their functionality for applications in high density, energy-efficient high-performance computing systems.

A Process-Tolerant Ring Modulator Based on Multi-Mode Waveguides

The next-generation servers and supercomputers with high performance and low power consumption require not only CPUs with an enhanced processing capability, but also signal transmission technology that connects CPUs with other CPUs or memories at high density and low power. It is becoming difficult for electrical signal transmission to satisfy the demand for the next-generation servers and supercomputers due to the decrease of transmission distance in high-speed transmission and the restriction of the numbers of pins. Therefore, there have been increasing expectations for optical interconnects enabling large-capacity (wide bandwidth) and long-distance transmission. Thus, there are high hopes that it will be a key technology. Especially, silicon (Si) photonic interconnects have been attracting much attention in recent years because they are considered to be promising for reducing the size, increasing integration density and lowering the power consumption of optical transceivers. This paper explains Fujitsu’s and Fujitsu Laboratories’ small, energy-efficient Si photonics optical trans ceiver technologies. The key factors for realizing a small, high-density optical transceiver with low power consumption involve enhancing optical devices and driver circuits, and optimizing the mounting structure to supply high-quality power and signals. We proposed a novel configuration for a Si photonic transceiver utilizing a bridge structure that enabled high-density integration without wiring, and we optimized the design of optical/electrical devices based on this structure. We achieved the world’s best performance in terms of high signal density and low power consumption, and demonstrated the effectiveness of the technology.

/pdf/silicon-photonics-optical-transceiver-for-high-speed-high-2he20mh63a.pdf

Silicon Photonics Optical Transceiver for High-speed, High-density and Low-power LSI Interconnect

We present a novel configuration of hybrid-integrated silicon photonic interconnects employing a bridge structure, and demonstrate 25 Gbps error-free operation between transmitter and receiver with power efficiency of 9.6 mW/Gbps including a serializer chip.

A 25 Gbps silicon photonic transmitter and receiver with a bridge structure for CPU interconnects

PROBLEM TO BE SOLVED: To improve monotonicity and/or linearity in an analog-to-digital converter.SOLUTION: The system comprises an array of comparators each for converting analog input into digital output, a switch formed to adjust output bits of the digital output, and a control logic part. The control logic part initializes the switch and initializes a DC source providing the analog input. The control logic part is formed to increase the DC source for the unit of an advancing stride of a minimum voltage value corresponding to a least significant bit of the digital output. The control logic part is also formed to cause the switch to adjust one or more output bits of the digital output at least partially based on a value of the output bit corresponding to a present advancing stride.

Control system, control method and storage medium

In one embodiment, a comparator of a Flash analog-to-digital converter (ADC) is calibrated in the background by switching the comparator to a feedback loop, determining the comparator's current reference level, and adjusting the comparator's reference level to a target reference level by charging a reference capacitor coupled the comparator.

Calibration scheme for resolution scaling, power scaling, variable input swing and comparator offset cancellation for flash ADCs

The present disclosure relates to a method of optimizing via cutouts, including selecting a geometry of a via cutout on a first ground reference layer adjacent to a first differential trace, the geometry selected to provide an extension region extending in the direction of the first differential trace. Additionally, the method includes the steps of selecting a geometry of the first differential trace, wherein a spacing of the first differential trace in the extension region is different from a spacing of the first differential trace outside the extension region, and selecting a radial dimension of a first and second via cutout on a second ground reference layer adjacent to and between the first and second differential traces, the radial dimension of the first via cutout and the second via cutout selected such that the second ground reference layer remains intact in the area adjacent the second differential trace.

Optimized via cutouts with ground references

A clock multiplication and distribution system includes a first phase-lock-loop circuit, a second phase-lock-loop circuit, and a clock distribution network that electrically couples the first phase-lock-loop circuit and the second phase-lock-loop circuit. The first phase-lock-loop circuit may include a first feedback loop that includes a first integer divider circuit and may be configured to generate a first clock using a reference clock. A frequency of the first clock may be greater than a frequency of the reference clock. The second phase-lock-loop circuit may include a second feedback loop that includes a second integer divider circuit and may be configured to generate a second clock using the first clock. A frequency of the second clock may be greater than the frequency of the first clock.

Clock multiplication and distribution

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