Embedded real-time software systems often need fine-grained parallelism and precise control over time, things typical real-time operating systems do not provide. The Esterel language has both, but Existing compilers produce slow code for large programs.This paper presents the first Esterel compiler able to produce small, fast code for large programs. It can produce code half the size and up to a hundred times faster than code from existing compilers. Esterel's semantics allow the compiler to statically schedule concurrency and synthesize code that efficiently and predictably simulates context switches. The main contribution is an algorithm that synthesizes an efficient sequential program from the concurrent control-flow graph used as an intermediate representation. These techniques could be applied to any language with fine-grained parallelism.

/pdf/compiling-esterel-into-sequential-code-5cmrqo3zmv.pdf

Compiling Esterel into sequential code

This paper presents a novel compiler for Esterel, a concurrent synchronous imperative language. It generates fast, small object code by compiling away concurrency, producing a single C function requiring no operating system support for threads. It translates an Esterel program into an acyclic concurrent control-flow graph from which code is synthesized that runs instructions in an order respecting inter-thread communication. Exceptions and preemption constructs become conditional branches. Variables save control state; conditional branches restore it. Although designed for Esterel, this approach could be applied to compiling other synchronous concurrent languages.

/pdf/compiling-esterel-into-sequential-code-2z1yqgzf0y.pdf

Embedded systems have become integral parts of today's technology-based life, starting from various home appliances to satellites. Such a wide range of applications encourages for their economic design using optimization-based tools. The JPEG encoder is an embedded system, which is applied for obtaining high quality output from continuous-tone images. It has emerged in recent years as a problem of optimum partitioning of its various processes into hardware and software components. Realizing pairing and conflicting nature among its various cost terms, for the first time the JPEG encoder is formulated and partitioned here as a multi-objective optimization problem. A multi-objective binary-coded genetic algorithm is proposed for this purpose, whose effectiveness is demonstrated through the application to a real case study and a number of large-size hypothetical instances.

Multi-objective hardware-software partitioning of embedded systems: A case study of JPEG encoder

This paper addresses the problem of the predictability of the critical digital-signal acquisition and processing applications while interacting with signals. The hard real-time compact kernel (HARETICK) is briefly presented along with the model of the hard real-time tasks: the ModX. This paper focuses on the specification, analysis, scheduling, and implementation of the applications able to generate perfectly periodic signals on the HARETICK-based platforms. A specific nonpreemptive technique for scheduling a set of the ModXs with fixed-execution times during their periods-the fixed execution nonpreemptive (FENP) algorithm-was introduced. Some of the most interesting experimental results are also discussed.

Maximum predictability in signal interactions with HARETICK kernel

Embedded systems typically consist of application specific hardware parts and programmable parts, e.g. processors like DSPs, core processors or ASIPs. In comparison to the hardware parts, the software parts are much easier to develop and modify. Thus, software is less expensive in terms of costs and development time. Hardware, however, provides better performance. For this reason, a system designer's goal is to design a system fulfilling all system constraints. The co-design phase, during which the system specification is partitioned onto hardware and programmable parts of the target architecture, is called Hardware/Software partitioning. This phase represents one key issue during the design process of heterogeneous systems. Some early co-design approaches [Marrec et al. 1998, Cloute et al. 1999] carried out the HW/SW partitioning task manually. This manual approach is limited to small design problems with small number of constituent modules. Additionally, automatic Hardware/Software partitioning is of large interest because the problem itself is a very complex optimization problem. Varieties of Hardware/Software partitioning approaches are available in the literature. Following Nieman [1998], these approaches can be distinguished by the following aspects: 1. The complexity of the supported partitioning problem, e.g. whether the target architecture is fixed or optimized during partitioning. 2. The supported target architecture, e.g. single-processor or multi-processor, ASIC or FPGA-based hardware. 3. The application domain, e.g. either data-flow or control-flow dominated systems. 4. The optimization goal determined by the chosen cost function, e.g. hardware minimization under timing (performance) constraints, performance maximization under resource constraints, or low power solutions. 5. The optimization technique, including heuristic, probabilistic or exact methods, compared by computation time and the quality of results. 6. The optimization aspects, e.g. whether communication and/or hardware sharing are taken into account. 7. The granularity of the pieces for which costs are estimated for partitioning, e.g. granules at the statement, basic block, function, process or task level. 8. The estimation method itself, whether the estimations are computed by special estimation tools or by analyzing the results of synthesis tools and compilers.

/pdf/particle-swarm-optimization-for-hw-sw-partitioning-si4zfg9ql3.pdf

Particle Swarm Optimization for HW/SW Partitioning

Hardware/Software co-design is not a new idea, since designers have been used to mixing programmable and specific hardware components for algorithms implementation. However, with the growing complexity of systems, a computer-aided co-design methodology becomes essential. This paper presents an application of the avionics domain: the ARINC communication protocol interface system. The co-design approach is based on the POLIS framework, coupled with the Esterel specification language.

/pdf/hardware-software-co-design-of-an-avionics-communication-1wqnm0hpi3.pdf

Hardware/software co-design of an avionics communication protocol interface system: an industrial case study

A cold plate for cooling heat-generating components, includes two plates extending parallel to each other. A core is sandwiched between the two plates to form a sandwich structure, the core including a set of passages for passing a cooling fluid from a first edge to an opposite second edge of the sandwich structure. First and second fluid-tight joining members are disposed respectively on the first and second opposite edges of the sandwich structure, the first fluid-tight joining member including at least one inlet connector and the second fluid-tight joining member including at least one outlet connector for the passage of the cooling fluid. A method for use of the cold plate in particular as a structural part of an avionics equipment item is also provided.

Cold plate, forming in particular a structural part of an item of equipment having heat-generating components

An electronics structure includes at least one barrier impermeable to fine particles, interposed between at least one Electrical and/or Electronics (“E & E”) system and the frame of the structure. The barrier delimits, with the frame and the E & E system, a first area isolated from the outside of the electronics structure. The structure makes it possible to isolate sensitive electrical and electronic components from fine particles such as dust dispersed outside the electronics structure.

Electronics structure comprising at least one barrier impermeable to fine particles

A cold plate (30) for cooling heat generating components (20) comprises two plates (11) extending parallel to one another. A core (13) is sandwiched between the two plates (11) to form a sandwich structure, the core (13) comprising a plurality of flow channels (13a) of a cooling fluid from a first edge ( 10a) to a second opposite edge (10b) of the sandwich structure. First and second tight connection elements (31, 32) are disposed at first and second opposite edges respectively (10a, 10b) of the sandwich structure, the first waterproof connector member (31) having at least one input connector ( 33) and the second sealing connection element (32) having at least one outlet connector (34) for the circulation of cooling fluid. Use in particular of the cold plate (30) as a structural part of an avionics equipment.

Cold plate, in particular forming the structural portion of a device with heat-generating components

The invention concerns a method and devices for analyzing the feasibility of a computer system composed of subsystems, each having functions. After having determined the functional architecture of the computer system comprising at least one subsystem and at least one function, the characteristics of the functions implemented are imported from a database. The user determines the number of subsystems and the number of connectors per subsystem. He then distributes the functions to the subsystems and enters the characteristics of the connectors and the characteristics of the subsystems. The computer system is analyzed in light of the information provided by the user and the characteristics of the functions implemented in order to determine the feasibility of the computer system.

Method and devices to assist in determining the feasibility of a computer system

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