60GHz and 80GHz-band power amplifier (PA) MMICs have been developed on a standard 90nm CMOS technology for use in RF front-ends of wide-band, low-cost communication and/or radar systems. A 60GHz three-stage PA and a 80GHz five-stage PA, both with single-ended architecture, have demonstrated saturated output powers of 12.6dBm and 10.3dBm with linear gains of 10.0dB and 12.2dB, respectively, the highest P sat 's reported to our best knowledge, under a 1.0V power supply voltage. The PA's were designed with systematically shifted cut-off frequencies of individual high-pass-type matching circuits to simultaneously achieve wide-band operations, resulting in demonstrated 1dB-gain bandwidth of 17GHz (55GHz to 72GHz), and 19GHz (66GHz to 85GHz), respectively.

60GHz and 80GHz wide band power amplifier MMICs in 90nm CMOS technology

A 20-24 GHz, fully integrated power amplifier (PA) with on-chip input and output matching is realized in 0.18 mum standard CMOS process. By cascading two cascode stages, the PA achieves 15 dB small signal gain, 10.7% power added efficiency, 16.8 dBm output saturation power and high power density per chip area of 0.137 W/mm2, which is believed to be the highest power density to our knowledge. The whole chip area with pads is 0.35 mm2, which is the smallest one compared to all reported paper.

A 20 to 24 GHz $+$ 16.8 dBm Fully Integrated Power Amplifier Using 0.18 $\mu{\rm m}$ CMOS Process

The integrated passive device (IPD) technology has become a new research hotspot, and it depends on electrical characteristics of GaAs, NiCr, and Si3N4 to construct radio frequency (RF) components. RF elements constructed by the IPD technology have features of high quality and ultra-small size, especially for capacitors and inductors. In order to realize the miniaturization of RF circuits, dimensions become as small as possible. Consequently, the layout of a spiral coupled line (SCL) cannot be drawn freely, so that it has uncontrollable odd- and even-mode impedances and a large coupling coefficient, which may limit the design of the traditional Marchand balun negatively. This article solves this problem by designing a GaAs IPD Marchand balun with 1/8-wavelength coupled lines (CLs) and using a capacitor termination to replace the open end in the conventional Marchand balun. Meanwhile, a filter is added to realize a filtering function. The proposed bandpass filtering Marchand balun (BFMB) chip has a size of 1.49 mm $\times1.39$ mm, and measured results indicate that it has an operation band of 2.39–5.68 GHz with a phase imbalance of 5.26° and a magnitude imbalance of less than 0.35 dB.

An Ultraminiaturized Bandpass Filtering Marchand Balun Chip With Spiral Coupled Lines Based on GaAs Integrated Passive Device Technology

A fully integrated 24 GHz 22 dBm power amplifier was designed and fabricated in 0.18-µm CMOS technology. Optimized device size selection and resonance matching techniques are adopted in this single stage power amplifier design. High pass matching circuit is used to reduce output losses and maintain gain flatness. The measurement results shows a 22 dBm of saturation power and 20 dBm of output power at 1 dB compression point with peak PAE of 20 % under 3.6 V bias supply. To the best of author's knowledge, this PA demonstrates the highest output power and highest PAE at 1 dB compression among the reported PAs in this frequency range using CMOS technology.

A 22-dBm 24-GHz power amplifier using 0.18-µm CMOS technology

This paper presents the design of a broadband power amplifier (PA) in 130-nm SiGe BiCMOS technology. First, a single-stage broadband single-cell PA covering the 4.5–18-GHz frequency band is introduced. In this frequency range, this single cell achieves a measured gain, saturated output power $({ P}_{\rm sat})$ , output 1-dB compression point $({ P}_{1{\rm dB}})$ , and power-added efficiency (PAE) in the range from 12.8 to 15.7 dB, 18.8 to 23.7 dBm, 16.7 to 19.5 dBm, and 11.4 to 31.9%, respectively. Its peak saturated output power and maximum PAE are both obtained at 8.5 GHz. Second, to increase the output power, a PA consisting of two parallel broadband cells with a power combination is presented. This PA operates in the 4.5–15.5-GHz frequency range with measured gain, ${ P}_{\rm sat}, { P}_{1{\rm dB}}$ , and PAE in the range from 11 to 16.6 dB, 21.3 to 25.5 dBm, 18.7 to 21.7 dBm, and 11.9 to 28.7%, respectively. It achieves its peak saturated output power of 25.5 dBm at 8.5 GHz and its maximum PAE of 28.7% with an associated output power of 23.6 dBm at 6.5 GHz. Each of those two PAs achieves better performances than the state-of-the-art in broadband SiGe technology when comparing the output power level and efficiency.

A Broadband 4.5–15.5-GHz SiGe Power Amplifier With 25.5-dBm Peak Saturated Output Power and 28.7% Maximum PAE

Two versions of power amplifiers with different output matching approaches for the 17-GHz band were realized in 0.13-mum standard digital CMOS technology with 1.5-V supply voltage. The power amplifier with an external matching network delivers 17.8-dBm saturated output power with 15.6% power added efficiency (PAE). The small-signal gain is 11.5 dB. The fully integrated power amplifier delivers 17.1-dBm saturated output power with 9.3% PAE. The small-signal gain is 14.5 dB. No external radio frequency components are required

17-GHz 50-60 mW power amplifiers in 0.13-/spl mu/m standard CMOS

A power amplifier for a frequency range of 11-13 GHz that is incorporated in 0.35 μm SiGe-technology is presented in this letter. The two-stage push-pull amplifier uses monolithically integrated transformers for input and interstage matching and a monolithically integrated modified LC-balun as an output-matching network. For stabilization purposes and gain improvement in the operating frequency range a passive frequency selective feedback in parallel to the base-collector was introduced. The power amplifier is mounted on a 7 × 7 mm VQFN package. From a single 1.8 V voltage supply, the amplifier has a power-added efficiency of greater than 30% from 11.2 to 13 GHz with a maximum of 37.3% at 12.5 GHz. The maximum output power is 23.4 dBm (saturation), as measured in the continuous mode.

Highly Efficient Packaged 11–13 GHz Power Amplifier in SiGe-Technology With 37.3% of PAE

In this paper a fully monolithically integrated power amplifier for X-band is presented. The push-pull amplifier uses an on-chip transformer for input matching, an autotransformer with capacitive divider for interstage matching, and an LC-balun for output matching. It does not require any external matching circuits. The power amplifier is implemented in a 0.35 µm SiGe bipolar technology. At 10 GHz operating frequency and a supply voltage of 1.5 V the amplifier achieves maximum power added efficiency greater than 30%, gain 23 dB, and maximum output power greater than 23 dBm.

Fully monolithically integrated X-band power amplifier without external matching

This paper presents a low noise amplifier (LNA) with differential output using a passive frequency selective feedback. The introduced feedback stabilizes the amplifier at lower frequencies and improves the gain in the desired frequency band. The LNA consists of two stages. Additionally, a buffer at the output is added for measurements. The amplifier was implemented in a 0.35 μm SiGe technology. For measurements the LNA was bonded to a substrate. A peak gain of 28.1 dB and a minimum noise figure of 2.2 dB at a supply voltage of 3 V were achieved.

A Narrow-band 8.7 GHz SiGe HBT LNA with a Passive Frequency Selective Feedback

Monolithically integrated fractional-N frequency synthesiser controlled by the dual edge triggered (DET) MASH ΣΔ modulator is presented. A DET modulator offers two advantages over the single edge triggered implementation: (1) it reduces the modulator's area by 15–20% and (2) it distributes switching noise power in such a manner that it does not degrade the first reference spur of a synthesiser but shifts the glitch energy to higher multiples of the reference frequency. A benefit of such a reference spur power distribution is demonstrated. A fabricated 11 GHz fully integrated sigma–delta phase-locked loop (PLL) with the DET modulator exhibits the first reference spur below –66 dBc over the whole locking range.

Monolithically integrated SD frequency synthesiser with distributed reference spurs

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