Process variations and device aging impose profound challenges for circuit designers. Without a precise understanding of the impact of variations on the delay of circuit paths, guardbands, which keep timing violations at bay, cannot be correctly estimated. This problem is exacerbated for advanced technology nodes, where transistor dimensions reach atomic levels and established margins are severely constrained. Hence, traditional worst-case analysis becomes impractical, resulting in intolerable performance overheads. Contrarily, process-variation/aging-aware static timing analysis (STA) equips designers with accurate statistical delay distributions. Timing guardbands that are small, yet sufficient, can then be effectively estimated. However, such analysis is costly as it requires intensive Monte-Carlo simulations. Further, it necessitates access to confidential physics-based aging models to generate the standard-cell libraries required for STA. In this work, we employ graph neural networks (GNNs) to accurately estimate the impact of process variations and device aging on the delay of any path within a circuit. Our proposed GNN4REL framework empowers designers to perform rapid and accurate reliability estimations without accessing transistor models, standard-cell libraries, or even STA; these components are all incorporated into the GNN model via training by the foundry. Specifically, GNN4REL is trained on a FinFET technology model that is calibrated against industrial 14-nm measurement data. Through our extensive experiments on EPFL and ITC-99 benchmarks, as well as RISC-V processors, we successfully estimate delay degradations of all paths—notably within seconds—with a mean absolute error down to 0.01 percentage points. 

/pdf/gnn4rel-graph-neural-networks-for-predicting-circuit-2tgvlndw.pdf

GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation

Traditional timing analysis employs a delay model that assumes only a single input switches for a gate during a transition, while all side inputs are held constant to noncontrolling values. However, ignoring the impact of multiple-input switching (MIS) can lead to either an overestimation or an underestimation of a gate delay. In this article, we examine the impact of MIS in the delay of different types of gates under varying conditions of load, slew, and temporal distance of signals at the inputs. We model the impact of MIS by deriving a corrective measure that should be applied to the conventional single-input switching (SIS) delay under different conditions. We call this corrective measure as MIS-SIS difference (MSD). In this work, we have evaluated polynomial regressions, support vector regression, and artificial neural networks (ANNs) to model MSD. Additionally, we integrate the ANN-based MSD model into existing timing libraries and employ them in carrying out MIS-aware timing analysis. We test the proposed methodology on some benchmark circuits and demonstrate that the proposed technique can improve the accuracy of timing analysis effectively. For example, for ISCAS’85 C17 circuit having short paths, under the MIS scenario, traditional SIS-based delay differs from the corresponding SPICE-computed delay by as large as 120%. However, the delay computed using the proposed methodology under the MIS scenario for the same circuit differs from the SPICE-computed delay by less than 3%. Additionally, the runtime overhead of the proposed methodology during timing analysis is negligible.

Modeling Multiple-Input Switching in Timing Analysis Using Machine Learning

Process variations and device aging impose profound challenges for circuit designers. Without a precise understanding of the impact of variations on the delay of circuit paths, guardbands, which keep timing violations at bay, cannot be correctly estimated. This problem is exacerbated for advanced technology nodes, where transistor dimensions reach atomic levels and established margins are severely constrained. Hence, traditional worst-case analysis becomes impractical, resulting in intolerable performance overheads. Contrarily, process-variation/aging-aware static timing analysis (STA) equips designers with accurate statistical delay distributions. Timing guardbands that are small, yet sufficient, can then be effectively estimated. However, such analysis is costly as it requires intensive Monte-Carlo simulations. Further, it necessitates access to confidential physics-based aging models to generate the standard-cell libraries required for STA. In this work, we employ graph neural networks (GNNs) to accurately estimate the impact of process variations and device aging on the delay of any path within a circuit. Our proposed GNN4REL framework empowers designers to perform rapid and accurate reliability estimations without accessing transistor models, standard-cell libraries, or even STA; these components are all incorporated into the GNN model via training by the foundry. Specifically, GNN4REL is trained on a FinFET technology model that is calibrated against industrial 14-nm measurement data. Through our extensive experiments on EPFL and ITC-99 benchmarks, as well as RISC-V processors, we successfully estimate delay degradations of all paths—notably within seconds—with a mean absolute error down to 0.01 percentage points.

Accurate standard cell modeling is significant for circuit timing analysis and yield estimation. With voltage decreasing to near-threshold, cell delay distribution becomes asymmetrical and has a longer tail due to various process variation effects. In this brief, we propose a novel statistical model to fit the shape of the cell delay by using log-extended-skew-normal (LESN) distribution. It estimates the values of mean, standard deviation, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\sigma $ </tex-math></inline-formula> delay precisely by matching the kurtosis of the cell delay distribution. By changing the parameters of the LESN model, it can be used for up to the normal voltage region (1.1V) and down to the sub-threshold voltage region (0.4V). Considering the effect of load capacitances, the parameters of LESN distribution are further modeled so that the model can be used for different fanout constraints. Tested by INV, NAND2, and NOR2 with 28 nm technology, the average error of estimating the skewness is less than 6%, while the error for the kurtosis is less than 4%. Meanwhile, the average errors of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-3\sigma $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$+3\sigma $ </tex-math></inline-formula> delay estimation are about 1.27% and 1.82% from 0.4V to 1.1V, respectively. 

A Statistical Cell Delay Model for Estimating the 3σ Delay by Matching Kurtosis

Near-threshold computing has emerged as a promising solution for drastically improving the energy efficiency of microprocessors. This paper proposes architectural-level statistical static timing analysis (SSTA) models for the near-threshold voltage computing where the path delay distribution is approximated as a lognormal distribution. First, we prove several important theorems that help consider architectural design strategies for high performance and energy efficient near-threshold computing. After that, we show the numerical experiments with Monte Carlo simulations using a commercial 28-nm process technology model and demonstrate that the properties presented in the theorems hold for the practical near-threshold logic circuits.

Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design

The increasing performance variation poses remarkable challenges to timing analysis for circuits operating in near-threshold voltage (NTV) region in spite of attractive energy efficiency advantage. Few researches were devoted to the statistical timing model for NTV design especially when input transition time was considered. In this paper, a statistical timing model for CMOS inverter is proposed in NTV region under process variation considering fast and slow input, which is derived analytically with a novel segmented step approximation method to overcome the integral issue of drain current equation for ramp input. The mean and variance of inverter delay distribution are derived as a function of the supply voltage, inverter size, load capacitance, and input transition time with the statistical characteristics of process variation. Experimental results under 40nm process show that the proposed inverter delay model is highly fitted with Monte Carlo (MC) simulation results at the supply voltage of 0.4V, where the mean and variance error are less than 5.35% and 8.36% for fast input and 10.89% and 13.07% for slow input respectively.

A Statistical Timing Model for CMOS Inverter in Near-threshold Region Considering Input Transition Time

Path delay variation becomes a serious concern in advanced technology, especially for multi-corner conditions. Plenty of timing analysis methods have been proposed to solve the issue of path delay variation, but they mainly focus on every single corner and are based on a characterized timing library, which neglects the correlation among multiple corners, resulting in a high characterization effort for all required corners. Here, a novel prediction framework is proposed for path delay variation by employing a learning-based method using back propagation (BP) regression. It can be used to solve the issue of path delay variation prediction under a single corner. Moreover, for multi-corner conditions, the proposed framework can be further expanded to predict corners that are not included in the training set. Experimental results show that the proposed model outperforms the traditional Advanced On-Chip Variation (AOCV) method with 1.4X improvement for the prediction of path delay variation for single corners. Additionally, while predicting new corners, the maximum error is 4.59%, which is less than current state-of-the-art works.

https://www.mdpi.com/2079-9292/9/1/157/pdf

Novel Prediction Framework for Path Delay Variation Based on Learning Method

The near-threshold design is widely employed in the energy-efficient circuits, but it suffers from a high sensitivity to process variation, which leads to 2X delay variation due to temperature effects. Hence, it is not negligible. In this paper, we propose an analytical model for gate delay variation considering temperature effects in the near-threshold region. The delay variation model is constructed based on the log-skew-normal distribution by moment matching. Moreover, to deal with complex gates, a multi-variate threshold voltage approximation approach of stacked transistors is proposed. Also, three delay metrics (delay variability, ± 3 σ percentile points) are quantified and have a comparison with other known works. Experimental results show that the maximum of delay variability is 5% compared with Monte Carlo simulation and improves 5X in stacked gates compared with lognormal distribution. Additionally, it is worth mentioning that, the proposed model exhibits excellent advantages on − 3 σ and stacked gates, which improves 5X–10X in accuracy compared with other works.

https://www.mdpi.com/2079-9292/8/5/501/pdf

Analytical Gate Delay Variation Model with Temperature Effects in Near-Threshold Region Based on Log-Skew-Normal Distribution

The interdependency of the setup and hold constraints and clock-to-q (c2q) delay for flip-flops (FF) has been studied in static timing analysis (STA) to facilitate timing closure and improve circuit performance. However circuits operating in near-threshold voltage (NTV) region pose severe challenge to the interdependent timing modelling due to its significant nonlinear relation and much wider constraint range compared with super-threshold voltage (STV) region. In this paper an accurate and efficient modelling approach is proposed by employing artificial neuron network (ANN) to characterize the interdependency among the setup time hold time and c2q delay of FF in wide voltage region. Experimental results show the prediction errors of c2q delay with varied setup and hold constraints are lower than 2.1% and 1.8% in NTV and STV regions with 3.51x and 1.09x accuracy improvement compared with the prior work. Besides the modelling efficiency is validated by 1.41 x/1.10x simulation cost reduction and 21.08x/4.14x library storage saving for NTV/STV domain with accuracy advantage.

Accurate and Efficient Interdependent Timing Model for Flip-Flop in Wide Voltage Region

Path delay variation becomes a serious concern in advanced technology, especially at low supply voltage. Plenty of timing analysis methods have been proposed based on the characterized timing library, which neglects the correlation among multiple corners, resulting in high characterization effort for all required corners. In this paper, two machine learning-based models are proposed by limited SPICE simulations for artificial paths including back propagation (BP) and random forest (RF) regression. They can be employed to solve the issue of path delay variation prediction under the unknown corners which have not been characterized during the establishment the proposed models. Experimental results show that both models outperform the traditional AOCV method with higher accuracy for the prediction of path delay variation under multiple corners.

Path Delay Variation Prediction Model with Machine Learning

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