Delphi-like Boundary Condition Independent (BCI) Compact Thermal Models (CTMs) are the standard for modelling single die packages. However their extraction, particularly in the transient case, will be time consuming due to complex numerical simulations for a large number of external conditions. Lately, new approaches to extract a BCI Dynamical CTM (DCTM), based on Model Order Reduction (MOR) have been developed. Despite the numerous advantages of this recent method, the lack of numerical tools to integrate reduced-order models (ROM) makes it difficult to use at board level. In this study, a novel process flow for extracting Delphi-inspired BCI DCTMs is investigated. Thus a detailed three-dimensional model is replaced by a BCI-ROM model using FANTASTIC matrix reduction code to generate the data used in the creation of a Delphi-style BCI DCTM. That hybrid reduction method has been applied to an industrial single-chip package, named QFN16. Its derived CTM and DCTM have been compared in term of accuracy and creation time for both approaches: in-house Delphi-inspired and MOR based. The results show that for a similar accuracy, the integration of MOR technique allows minimizing the time-consuming numerical simulations and so to reduce the thermal network creation time by 80%.

Delphi-like dynamical compact thermal models using model order reduction

Nowadays, thermal designers have to deal with sophisticated 3D component packaging, enclosing several chips or conventional individually-packaged Integrated circuits with various power densities, embedded in small volumes that will drive up the complexity of their thermal management. Previous analyses were made on system-in-package (SIP) modules to better know the thermal behavior of its encapsulated chips as well as the ability to create a Compact Thermal Model with numerous power sources. These works demonstrated that the creation of thermal resistance networks with n sources, compliant with a large set of realistic boundary conditions, can be achieved with success using superposition principle and Genetic Algorithm (GA) fitting technique. To pursue the development of effective thermal models for DC-DC converter devices, a set of experiments was performed to assess the pertinence of numerical simulations. Thus the upper surface of the asymmetric side-by-sidechips package was subdivided to characterize a set of local maximal and average temperatures. The temperature predictions of the numerical models were compared with the experimental infrared results. The present work describes the process flow that has to be led to generate a detailed numerical model having a low divergence with experimental results. It also declines the creation of DELPHI style models of the discrete sensitive parts of the package, such as inductor device. Each deducted network predicts the monitored key temperatures of the detailed thermal model with a discrepancy lower than 10%. Further a reduction methodology which nests these SubCompact Thermal Models promotes an alternative solution to realize more quickly the generation of a multiple sources thermal resistance networks, according to the boundary condition independent concept [3]. Therefore, the paper summarizes the comparison of a "state-of-the-art" numerical detailed model and its deducted compact model with the help of infrared experimental results in order to establish a modeling guideline.

Latest developments of compact thermal modeling of system-in-package devices by means of Genetic Algorithm

The Compact Thermal Models (CTMs) became a standard for low-cost modeling of single-chip electronic packages. According with Delphi's method, their creation is time consuming since numerical simulations of a Detailed Thermal Models (DTMs) of the package have to be repeated for large sets of Robin's Boundary Conditions (BCs). Moreover Jedec standards do not provide guidance to consider multi-chip packages or to investigate the creation of multi-path transient behavioral models. The present study proposes a complementary method to create Dynamical Delphi-style CTMs (DCTMs acronym). This one promotes the replacing of the heavy computational simulations of a given detailed model by a faster reduced order model, built by the means of modal approach. At first, that multi-stage reduction method is applied with success to a single-chip package (QFN16) then to a dual-chip package (DFN12). As relevant results, the mathematical computation time is drastically shortened, which allows speeding up the DCTM creation procedure by 80%, without degrading its accuracy.

Delphi-like dynamical compact thermal models using model order reduction based on modal approach

Purpose




Latest Computational Fluid Dynamics (CFDs) tools allow modeling more finely the conjugate thermo-fluidic behavior of a single electronic component mounted on a Printed Wiring Board (PWB). A realistic three-dimensional representation of a large set of electric copper traces of its composite structure is henceforth achievable. The purpose of this study is to confront the predictions of the fully detailed numerical model of an electronic board to a set of experiment results to assess their relevance.




Design/methodology/approach




The present study focuses on the case of a Ball Grid Array (BGA) package of 208 solder balls that connect the component electronic chip to the Printed Wiring Board. Its complete geometrical definition has to be coupled with a realistic board layers layout and a fine description of their numerous copper traces to appropriately predict the way the heat is spread throughout that multi-layer composite structure. The numerical model computations were conducted on four CFD software then compare to experiment results. The component thermal metrics for single-chip packages are based on the standard promoted by the Joint Electron Device Engineering Council (JEDEC), named JESD-51. The agreement of the numerical predictions and measurements has been done for free and forced convection.




Findings




The present work shows that the numerical model error is lower than 2 per cent for various convective boundary conditions. Moreover, the establishment of realistic numerical models of electronic components permits to properly apprehend multi-physics design issues, such as joule heating effect in copper traces. Moreover, the practical modeling assumptions, such as effective thermal conductivity calculation, used since decades, for characterizing the thermal performances of an electronic component were tested and appeared to be tricky. A new approach based on an effective thermal conductivity matrix is investigated to reduce computation time. The obtained numerical results highlight a good agreement with experimental data.




Research limitations/implications




The study highlights that the board three-dimensional modeling is mandatory to properly match the set of experiment results. The conventional approach based on a single homogenous layer using effective thermal conductivity calculation has to be banned.




Practical implications




The thermal design of complex electronic components is henceforth under increasing control. For instance, the impact of gold wire-bonds can now be investigated. The three-dimensional geometry of sophisticated packages, such as in BGA family, can be imported with all its internal details as well as those of its associated test board to build a realistic numerical model. The establishment of behavioral models such as DELPHI Compact Thermal Models can be performed on a consistent three-dimensional representation with the aim to minimize computation time.




Originality/value




The study highlights that multi-layer copper trace plane discretization could be used to strongly reduce computation time while conserving a high accuracy level.

State of the art of thermal characterization of electronic components using computational fluid dynamic tools

Impact of Printed Circuit Board Via and Micro-Via Structures on Component Thermal Performances

Emerging packages offer diverse options for mounting active and passive devices in a single package, such as side by side, embedded or stacked die placements.

Delphi style compact modeling for multi-chip package including its bottom board area based on genetic algorithm optimization

The thermal dissipation challenges that are seen today with single-chip components will only be magnified with the introduction of System in Package devices.

Thermal modelling of the emerging multi-chip packages

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Delphi style compact modeling for multi-chip package including its bottom board area based on genetic algorithm optimization

Thermal modelling of the emerging multi-chip packages