A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive unproductive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

Altering thread priorities in a multithreaded processor

A virtual storage system for use in conjunction with a host computer is disclosed. The system features a memory control processor external to the host computer which divides user-defined data sets into blocks of a size convenient for storage on, e.g., magnetic media and individually assigns these blocks to locations determined external to the host. In this way, the extent of a particular data file is not specified by the user; nor is empty space allocated in anticipation of future use. The virtual memory system may additionally comprise a high speed cache memory for receiving data written to the memory system at high speed from the host. Data anticipated to be the subject of future requests can be staged to the cache, so that it can be supplied to the host at high speed, thus improving system performance. Data compression and decompression may be incorporated in the storage system. Numerous data back-up and automated recovery processing operations may additionally be performed by this system without specific instruction from the host.

Virtual storage system and method

A robust optoelectronic transceiver module which is quick, easy, and inexpensive to manufacture. The transceiver module has a main housing which consists of a potting box with potting material inserted therein. In addition, a circuit board is encased by the potting material. The circuit board has an optical subassembly mounted thereon. The optical subassembly extends outside of the potting box through a recess. Correspondingly, a recess cover is provided for forming a liquid tight seal between the recess cover, the potting box, and the optical subassembly. The module housing may be pluggable via release levers having detentes received in apertures of a receptacle and a pluggable connector of the module mated within the receptacle. The receptacle may include grounding means such as a ground clip mounted within the receptacle and a protective door to limit electromagnetic emissions.

Removable transceiver module and receptacle

A system and method for performing computer processing operations in a data processing system includes a multithreaded processor (110) and thread switch logic (400) The multithreaded processor (110) is capable of switching between two or more threads of instructions which can be independently executed Each thread has a corresponding state in a thread state register (440) depending on its execution status The thread switch logic contains a thread switch control register (410) to store the conditions upon which a thread switch can occur Upon the occurrence of a thread switch event, the state and priority of all threads are dynamically interrogated to determine which thread should be the active thread executing the processor The thread switch logic has a time-out register (430) which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time Thread switch logic also has a forward progress count register (420) to prevent repetitive unproductive thread switching between threads in the multithreaded processor Thread switch logic also is responsive to a thread switch manager (460) capable of changing the priority of the different threads and thus superseding thread switch events

Thread switch control in a multithreaded processor system

A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

Method and apparatus to force a thread switch in a multithreaded processor

A system and method for computer process dispatching in a multiprogramming/multiprocessing environment is disclosed. Each process in the multiprogramming/multiprocessing computer system may be in one of four states at any given time as follows: 1. Running -- the process is in control of the computer system and is directing the operation of the central processing unit (CPU); 2. ready -- the process is ready to run as soon as it is given control of the CPU; 3. waiting -- the process is waiting for an external event to occur so it can either resume running or enter the ready state; 4. Suspended -- the process has been temporarily stopped (from a source external to the process). The dispatcher is a firmware/hardware structure that controls the first three states of the process--i.e. running, ready and waiting states.

Process management structures and hardware/firmware control

A method of and apparatus for executing a family of instructions provides synchronization of processes in a multiprocessing system. Representations of processes awaiting data (information units) such as the completion of an asynchronous operation or the availability of a resource are stored in a memory in a first queue and representations of information units available to processes are stored in memory in a second queue. Transfer of information units between processes is controlled by data elements known as "semaphores" stored in the memory. Each semaphore contains a field having a numerical value identifying which of the two different kinds of queues is present. When a P instruction is executed by a process indicating that the process requires data in order to continue operating or a V instruction is executed indicating that an information unit is available for transfer to another process, a semaphore is addresses and its field tested to determine whether processes or information units are available to enable the information transfer between processes to be effected. Once the information transfer is completed, the field of the addressed semaphore is up-dated.

Apparatus and method for transferring information units between processes in a multiprocessing system

An information structure, or semaphore, serves as a signalling mechanism in process synchronization to connect a process and a non-simultaneously occurring event or resource. The semaphore is a data structure which stores representations of processes awaiting particular events or alternatively stores representations of events awaiting processes. Semaphore data structures are developed in two storage areas. First and second groups of process links are stored in the first storage area to establish, respectively, a first queue of processes ready to operate and a second queue, associated with the semaphore structure, of processes awaiting occurrences of a first particular event prior to being ready to operate. In the second storage area are stored first and second groups of message links to establish respectively a first queue, associated with a semaphore structure, representing second particular events and a second queue of unused links. A signal is generated in response to operation of a first process to denote the occurrence of a first event. In response to the signal, the first event is associated with a process represented by a process link in the second queue of process links when the first event is the first particular event. When no queue has a process link identifying a process awaiting the occurrence of the first event, a representation of the first event occurrence is stored in a message link of the second queue of message links to be transferred to the first queue of message links. Process and event occurrence representations are thus transferred among the process and event queues during synchronization that takes place between the processes and events.

Apparatus and method for providing synchronization between processes and events occurring at different times in a data processing system

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Process management structures and hardware/firmware control

Apparatus and method for transferring information units between processes in a multiprocessing system

Apparatus and method for providing synchronization between processes and events occurring at different times in a data processing system