Spins in silicon quantum devices are promising candidates for large-scale quantum computing. Gate-based sensing of spin qubits offers a compact and scalable readout with high fidelity, however, further improvements in sensitivity are required to meet the fidelity thresholds and measurement timescales needed for the implementation of fast feedback in error correction protocols. Here, we combine radio-frequency gate-based sensing at 622 MHz with a Josephson parametric amplifier, that operates in the 500--800 MHz band, to reduce the integration time required to read the state of a silicon double quantum dot formed in a nanowire transistor. Based on our achieved signal-to-noise ratio, we estimate that singlet-triplet single-shot readout with an average fidelity of 99.7% could be performed in $1\text{ }\text{ }\ensuremath{\mu}\mathrm{s}$, well below the requirements for fault-tolerant readout and 30 times faster than without the Josephson parametric amplifier. Additionally, the Josephson parametric amplifier allows operation at a lower radio-frequency power while maintaining identical signal-to-noise ratio. We determine a noise temperature of 200 mK with a contribution from the Josephson parametric amplifier (25%), cryogenic amplifier (25%) and the resonator (50%), showing routes to further increase the readout speed.

Fast Gate-Based Readout of Silicon Quantum Dots Using Josephson Parametric Amplification.

Quantum error correction is vital for implementing universal quantum computing. A key component is the encoding circuit that maps a product state of physical qubits into the encoded multipartite entangled logical state. Known methods are typically not 'optimal' either in terms of the circuit depth (and therefore the error burden) or the specifics of the target platform, i.e. the native gates and topology of a system. This work introduces a variational compiler for efficiently finding the encoding circuit of general quantum error correcting codes with given quantum hardware. Focusing on the noisy intermediate scale quantum regime, we show how to systematically compile the circuit following an optimising process seeking to minimise the number of noisy operations that are allowed by the noisy quantum hardware or to obtain the highest fidelity of the encoded state with noisy gates. We demonstrate our method by deriving novel encoders for logic states of the five qubit code and the seven qubit Steane code. We describe ways to augment the discovered circuits with error detection. Our method is applicable quite generally for compiling the encoding circuits of quantum error correcting codes.

/pdf/variational-circuit-compiler-for-quantum-error-correction-2yb2mwyxzx.pdf

Variational circuit compiler for quantum error correction

Now that it is possible to achieve measurement and control fidelities for individual quantum bits (qubits) above the threshold for fault tolerance, attention is moving towards the difficult task of scaling up the number of physical qubits to the large numbers that are needed for fault-tolerant quantum computing. In this context, quantum-dot-based spin qubits could have substantial advantages over other types of qubit owing to their potential for all-electrical operation and ability to be integrated at high density onto an industrial platform. Initialization, readout and single- and two-qubit gates have been demonstrated in various quantum-dot-based qubit representations. However, as seen with small-scale demonstrations of quantum computers using other types of qubit, combining these elements leads to challenges related to qubit crosstalk, state leakage, calibration and control hardware. Here we overcome these challenges by using carefully designed control techniques to demonstrate a programmable two-qubit quantum processor in a silicon device that can perform the Deutsch–Josza algorithm and the Grover search algorithm—canonical examples of quantum algorithms that outperform their classical analogues. We characterize the entanglement in our processor by using quantum-state tomography of Bell states, measuring state fidelities of 85–89 per cent and concurrences of 73–82 per cent. These results pave the way for larger-scale quantum computers that use spins confined to quantum dots.

A programmable two-qubit quantum processor in silicon

We report the dispersive readout of the spin state of a double quantum dot formed at the corner states of a silicon nanowire field-effect transistor. Two face-to-face top-gate electrodes allow us to independently tune the charge occupation of the quantum dot system down to the few-electron limit. We measure the charge stability of the double quantum dot in DC transport as well as dispersively via in-situ gate-based radio frequency reflectometry, where one top-gate electrode is connected to a resonator. The latter removes the need for external charge sensors in quantum computing architectures and provides a compact way to readout the dispersive shift caused by changes in the quantum capacitance during interdot charge transitions. Here, we observe Pauli spin-blockade in the high-frequency response of the circuit at finite magnetic fields between singlet and triplet states. The blockade is lifted at higher magnetic fields when intra-dot triplet states become the ground state configuration. A lineshape analysis of the dispersive phase shift reveals furthermore an intradot valley-orbit splitting $\Delta_{vo}$ of 145 $\mu$eV. Our results open up the possibility to operate compact CMOS technology as a singlet-triplet qubit and make split-gate silicon nanowire architectures an ideal candidate for the study of spin dynamics.

Dispersively detected Pauli Spin-Blockade in a Silicon Nanowire Field-Effect Transistor

Quantum computers are far more error-prone than their classical counterparts. Therefore, to build a quantum computer capable of running large-scale quantum algorithms, we must use the techniques of quantum error correction to ensure that the computer produces the correct output even when its components are unreliable. However, the resource requirements of building such a fault-tolerant quantum computer are currently prohibitive. Here, we examine the utility of using three-dimensional (3D) surface codes in a fault-tolerant quantum computer. This family of topological error-correcting codes is a generalization of the well-known 2D surface code to three spatial dimensions. We show that certain 3D surface codes have a transversal logical non-Clifford gate. In a quantum computing architecture, a non-Clifford gate is required to achieve computational universality. Transversal gates do not entangle qubits in different codes, so they are naturally fault tolerant because they do not spread errors. Next, we consider the problem of decoding 3D surface codes. In a quantum error-correcting code, we cannot observe the qubits directly, so we measure parity-check operators to gain information about the state of the code. Decoding is the problem of estimating what error has occurred given a list of unsatisfied parity checks. We observe that 3D surface codes offer asymmetric protection against bit-flip and phase-flip errors, but in both cases, we find that a threshold error rate exists below which we can suppress logical errors by increasing the size of the code. We use our results about logical gates and decoding to propose two fault-tolerant quantum computing architectures that utilize 3D surface codes. Finally, we compare the resource requirements of our architectures with the requirements of leading quantum computing architectures based on topological codes. We find that one of our architectures may be competitive with the leading architectures, depending on the properties of the physical systems used to build the qubits.

Fault-tolerant quantum computing with three-dimensional surface codes

Spin qubits in silicon quantum dots are one of the most promising building blocks for large scale quantum computers thanks to their high qubit density and compatibility with the existing semiconductor technologies. High fidelity single-qubit gates exceeding the threshold of error correction codes like the surface code have been demonstrated, while two-qubit gates have reached 98\% fidelity and are improving rapidly. However, there are other types of error --- such as charge leakage and propagation --- that may occur in quantum dot arrays and which cannot be corrected by quantum error correction codes, making them potentially damaging even when their probability is small. We propose a surface code architecture for silicon quantum dot spin qubits that is robust against leakage errors by incorporating multi-electron mediator dots. Charge leakage in the qubit dots is transferred to the mediator dots via charge relaxation processes and then removed using charge reservoirs attached to the mediators. A stabiliser-check cycle, optimised for our hardware, then removes the correlations between the residual physical errors. Through simulations we obtain the surface code threshold for the charge leakage errors and show that in our architecture the damage due to charge leakage errors is reduced to a similar level to that of the usual depolarising gate noise. Spin leakage errors in our architecture are constrained to only ancilla qubits and can be removed during quantum error correction via reinitialisations of ancillae, which ensure the robustness of our architecture against spin leakage as well. Our use of an elongated mediator dots creates spaces throughout the quantum dot array for charge reservoirs, measuring devices and control gates, providing the scalability in the design.

/pdf/a-silicon-surface-code-architecture-resilient-against-g4yrz2wqih.pdf

A Silicon Surface Code Architecture Resilient Against Leakage Errors

Methods are disclosed for controlling charge stability in a device for quantum information processing. According to examples, a device for quantum information processing comprises a first plurality of confinement regions confining spinful charge carriers for use as qudits. The device further comprises a second plurality of confinement regions confining spinful charge carriers, each confinement region of the second plurality of confinement regions adjacent to a confinement region of the first plurality of confinement regions. The device further comprises one or more charge reservoirs, wherein each confinement region of the second plurality of confinement regions is attachable to a charge reservoir. According to examples, a method for controlling charge stability comprises selectively tuning the relative energy levels of the first plurality of confinement regions and adjacent confinement regions of the second plurality of confinement regions such that, if a spinful charge carrier leaks from a confinement region of the first plurality of confinement regions, then the spinful charge carrier is replaced to ensure that the confinement region of the first plurality of confinement regions again contains a spinful charge carrier for use as a qudit. Control apparatus and computer-readable media are also described herein.

Control of charge carriers in quantum information processing architectures

/pdf/a-silicon-surface-code-architecture-resilient-against-20mq7mpj2x.pdf

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A Silicon Surface Code Architecture Resilient Against Leakage Errors

Control of charge carriers in quantum information processing architectures

A Silicon Surface Code Architecture Resilient Against Leakage Errors